Alternative 4-layer Boards for High Speed PCBs

4-Layer Boards are among the most common high speed boards offered by manufacturers. But sometimes issues can arise with routing and signal integrity. In this video, Tech Consultant Zach Peterson explores these issues and offers a few alternative 4-layer boards for high speed PCBs.
0:00 Intro
1:49 A Standard 4-Layer Stackup
3:00 A Signal Integrity Problem
5:58 Return Current Issues
6:52 A Simple Solution
7:46 The First Alternative
11:25 The Second Alternative
15:29 An Important Consideration
For more Signal Integrity videos, click here: • Signal Integrity
For more PCB Routing videos, click here: • PCB Routing
For more PCB Design for Intermediate Users videos, click here: • PCB Design for Interme...
For more Technical Consultant Zach Peterson videos, click here: • Technical Consultant Z...
Two Alternative 4 Layer PCB Stackups With 50 Ohms Impedance: resources.altium.com/p/two-al...
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[@BS-my2ky]

Thank you so much. I love this teaching series!!!! Altium please transfer your advertisement budget to Altium Academy and Zach.

[@leeslevin7602]

Brilliant, thank you, I like the stack up topology with the 2 GND Planes located on the inner layers, I can definitely see the benefits.

[@vad2008vad]

Today is the day

[@str8upkickyaindanuts289]

One thing worth mentioning about the GND-SIG/PWR-SIG/PWR-GND stack-up when doing developmental work is the inability to break a problematic trace for a bodge wire. If one insists on using this stack-up it's advisable to make the via trace to IC pin accessible for alterations, in other words, don't place via's under the IC. It's becoming increasingly harder to "lift a pin" on modern packages for easy modifications without the need to respin a board. Unfortunately I learned this the hard way after watching the presentation by Rick Hartley showing the benefits of that stack-up.

[@Zachariah-Peterson]

Yeah that's a great point, I had not thought of that. But I guess you could do the prototype with sig on the outer layer, then flip it to the inner layer with trace width or layer thickness modifications, and do a 2nd prototype just to check crosstalk and functionality is identical to the 1st prototype, then put it into production.

[@nemoiy336]

Wow, that's an amazing and simple explanation I've ever heard, thank you very much!!!

[@AltiumAcademy]

Glad you enjoyed it!

[@Embedded_Developer]

Thank you very much for the lecture! it was very interesting to learn new things.

[@PankajKumar-zr3tv]

This guy is gold!

[@KevinStoriesTV]

great I learned again

[@m4l490n]

Thanks for addressing this!! This is a very useful follow-up. And now that you presented my comment I realize I should not have said never. You could certainly use a power plane. I just don't like to do it because then changing layers becomes a bit more complicated and expensive. I say complicated because when you use a power plane as reference, your signals should not change their reference between different power planes of different voltages, in other words, if a signal gets out of a chip using the 3.3V power plane as reference then this signal should not cross over a power plane of a different voltage and then use that as reference. You obviously can avoid this by having only one voltage but nowadays very few boards do, so it can\will get complicated. It is certainly easier to just use GND and not worry about, or even pay attention to, what's the power plane under the track all the time. I say expensive because when you change a reference plane from a power plane to a GND plane you would need a "stitching" capacitor for each signal that change reference planes. These stitching caps would help changing reference planes efficiently and keep the fields contained. So you would have to increase the amount of capacitors in a board and therefore the price. For a mixed-signal microcontroller board, really the best stackups are the last two you presented. I personally use the last one (SIG/PWR - GND - GND - SIG). This stackup allows to have absolutely all your signals on top and bottom always referenced to GND. Another very important point is that when a signal goes from top to bottom, you should ALWAYS put a gnd via (stitching via) as close as possible to the signal via to keep a constant and tight return path and to contain the fields. For power, on a talk with Rick Hartley he pointed out that in all 4-layer boards what he usually does is to fill both top and bottom layers with copper pour attached to power and have L2 and L3 as GND. Another option is to have power routed with tracks in the top layer only and give priority to these power tracks and lay them out first since you don't want the PDN going from top to bottom. Going from one layer to another needs vias that would increase the PDN inductance which is not good. For power integrity I usually scatter bulk electrolytic capacitors through the board and route the power in a star topology from them to different sections of the board as much as I can. When consulted this with Rick he pointed out that that is a good option since this method would help on keeping power on different board sections separated from one another thus preventing noise from a noisy part of the board from contaminating power on other sections. Something to keep in mind and implement if space permits.

[@robertbox5399]

Not sure electrolytics do anything at high frequencies. Ceramics are king these days. The former contain the water for the toilet, the latter allow the pistons to fire.

[@luisalvarado4591]

Wouldnt filling with copper top and bottom create crosstalk between pwr and signals?

[@m4l490n]

@@robertbox5399 yeah, they don't do much at high frequencies but is like having small batteries across the board. It is easier for the small high-frequency decoupling caps to get their charge from the nearest bulk electrolytic cap than all the way from the power supply. It's like going to the well instead of all the way to the lake.

[@saeedkizzy]

Hello, first of all, thanks Altium and you sir (Zach Petterson) for this series of training videos it really helps me to understand PCB design significantly. I have a question to ask: we can choose the correct track width and clearance for single-end and differential track but what about connectors how can we correct impedance mismatching caused by routing through connectors?

[@Zachariah-Peterson]

Hi Saeed, Connectors that are designed to support high speed or RF interconnects will be designed to a specific impedance value. For example, Samtec sells 50 Ohm SMA connectors that are used to route RF signals over a coaxial cable. Other companies sell similar products. If you need to apply some impedance matching, then you should consider a different connector, or you need to design to the connector impedance and then match at driver and receiver. It's best to try and find a connector that can support the standard impedance you need to route at.

[@saeedkizzy]

@@Zachariah-Peterson thanks for reply, in my project I use DF9 connector(1mm pitch) to route gigabit ethernet tracks is it ok to add gnd to adjacent pin to help return pass?

[@manojaa8338]

Informative 🤩

[@AltiumAcademy]

Glad you liked it

[@mitjasitar6751]

This video is great! However, I have a question. When you mention the stackup GND, SIG/PWR, SIG/PWR, GND - How does the SIG/PWR layer look like? Is the power also routed as a thick track between signal traces, or is it poured all over layer and that way connected to IC's? If it routed, then you have a small plane capacitance between GND and PWR? If it is poured, does it affect SI in signals in the same layer?

[@Zachariah-Peterson]

This is a good question! I seem to recall Rick Hartley saying to use copper pour on the component layer and just use that to connect to all components. If you do it as traces coming off a rail then yes you would have low capacitance, but that only becomes really important when you have a lot of digital, it would be fine for some lower frequency analog boards that take a DC input. Probably the best strategy with digital is to use a thin dielectric (8 mils or less) on the outer layer so that you can have thinner traces if you need impedance control, then you will have the freedom to use pour connected to power on the outer layer OR you could use traces. With a thicker dielectric on the outer layer, you will have to use coplanar routing to get to thinner traces and connect the coplanar region to GND.

[@unwatchable.]

Hi I like your video ... good explanation ... two questions ,, how far or near should the GND VIA from SIG VIA ? Secondly what about putting GND on second and PWR on third layer ... Third Question should the prepeg be in centre and cores under top n bottom ?

[@Zachariah-Peterson]

Hi Muhammad, 1. Ideally the GND via should be very close to the SIG via. Sometimes that might be difficult if you're routing between layers near other components, but I try to put it next to the signal via at just above the limits of clearances. 2. Doing that is fine, that is kind of the standard stackup where you have SIG/GND/PWR/SIG, just be careful to not route across the stackup without providing the return path between the top two layers. 3. Core is normally in the middle on standard stackups. If you want to do thick cores on the outer layer you can do that, but it provides less benefit for digital signals.

[@myetis1990]

Hi Zach, nice explanations, thank you. 14:15 "red via for return path" is it a via throughout between upper sig and lower sig layers? or is it just between two gnd layers?

[@Zachariah-Peterson]

Hi Mustafa, The red via is a through hole, so it accesses all layers, but is only connecting the GND planes.

[@myetis1990]

@@Zachariah-Peterson Thank you for your answer, can we call this method "via stitching"? if not, what is the difference?

[@Zachariah-Peterson]

@@myetis1990 Via stitching involves placing a regular array of vias around the board, usually to connect ground pour around your traces or to connect multiple planes. So if you have two internal GND planes, you could use via stitching to provide a low impedance connection between the two planes. I was referring to placing one ground via alongside the signal via. You can do both as the ground via next to the signal via will provide the smallest loop inductance return path. I would not use copper pour unless you have a good reason to do so. Generally when we have a strong wifi signal being emitted or received in the board, we'll use via stitching with copper pour to provide shielding, but the vias have to be spaced closely to provide the shielding effectiveness needed in the design.

[@saeidesekhavati1518]

It was very helpful thank you! I have a question, in SIG/GND plane/PWR plane/SIG type stackup, if I have a lots of digital signal, is there any solution through Via provide the return current? In this case should I use SIG/GND/GND/SIG?

[@Zachariah-Peterson]

You could have SIG/GND/PWR/(SIG + GND pour), and then place a grounded through via between the ground regions next to your via transitions. If you don't need a lot of current and you can manage to reach all of your components with power rails, then you could do SIG/GND/GND/SIG.

[@saeidesekhavati1518]

@@Zachariah-Peterson Thank you very much for answering me! It was very helpful!

[@DiegoColl44]

What would be the relative limit to start considering the return current of a signal in a PCB design...?? I assume that some signals is not relevant the return current. For example the signal of an indicator led.

[@Zachariah-Peterson]

Hi Diego, You always need to consider how you are routing return current. For your indicator LED, I would assume it's at DC, so there could be a large current loop in the design, depending on how you routed your ground. DC current won't produce radiation, but the loop that holds this current can receive radiation. The best way to deal with this is to use a dedicated rail that runs close to the LED power trace, or just use a ground plane. Using a ground plane is better. Thanks for watching!

[@rahulbanerjee5856]

Hi Zach, I thoroughly enjoyed your video. I am still very new to learning about PCB design. So, I am having some trouble visualising how a board can have components in an inner layer (layers 2 or 3 in a 4 layer stack up). Would you happen to have any diagrams or pictures where this can be illustrated?

[@hakanozturk7442]

You can not put any component in the inner layers which are layer 2 and layer 3 in a 4-layer board. The top and bottom layers are suitable for you to place components.

[@Zachariah-Peterson]

In the stackup where signals are placed on an inner layer, it doesn't mean that the components are on an inner layer. The components are on layers 1 and 4, and you get signals into the inner layers using vias. Hope this helps!

[@rahulbanerjee5856]

Thanks, that makes sense. So, to check my understanding, the signals are travelling along traces on the inner layer and the switching of layers for the signal is done by a via.

[@Zachariah-Peterson]

@@rahulbanerjee5856 Yes exactly, you might have a very short trace on the top layer that goes to a via, and then that via connects to the inner signal layer.

[@rahulbanerjee5856]

@@Zachariah-Peterson Thank you so much

[@TheVideoVolcano]

What about when you have a BGA? there is literally no space to do any transfer vias

[@Zachariah-Peterson]

With BGAs it is interesting because you have to hope that the component designer placed the I/Os such that the fastest I/Os are on the outer edge of the component and so they will not require transfer vias. This is what is often done on Ethernet controllers for example, the controllers we use have all the fastest I/Os along the edges so vias are not needed. For I/Os that are in the interior part of the BGA, there will be a slight impedance discontinuity looking into the via but it will not matter so much until bandwidths are very large. This might be challenging on, say, an FPGA, but you have a lot more freedom to place those interfaces on an FPGA because you get to configure the pins when designing your application.

[@romanleduc6007]

What about a 4 layer stackup GND-PwPlane-Sig-GND : shielding provided by outter layers , and no crosstalk / good impedance control between power and ground planes ? I suppose we are in the case where 1 signal layer is sufficient. Signal will be mostly coupled to close GND compared to Power so splitted power plane with different Vcc would not be too much to worry ?

[@Zachariah-Peterson]

If one layer is sufficient and your high-speed design will be operating in a high-noise environment, then your arrangement would work well. If I were going to do the design with components on both sides, I would make it PWR/GND/SIG/GND. I would put power-related components on the PWR layer so that they don't need vias to access the PWR nets, and I think this would be better for splitting DC nets as you'll need to make multiple connections direct to polygons. SIG on the inside is also good as the planes provide some shielding.

[@romanleduc6007]

​@@Zachariah-Peterson This is a legit stackup that I didn't think about / didn't see before and seems to be optimized regarding power purposes indeed. Thanks for your prompt answer & keep doing these great videos !

[@Maxime_Ethier]

Hi Zach, I'm a bit confused about one thing you mentionned, regarding the "GND / SIG-PWR / SIG-PWR / GND" stackup: Why would we need ground vias near signal vias, in order to couple the return path in the transitions between L1 and L2? If the dielectric between L1 and L2 is thin enough ( < 10 mils ), wouldn't the path of least impedance be to couple directly from L2 to L1? A ground via would probably be further away from the signal via, compared to the distance between the ground plane and the signal via. Also, I thought ground vias were only necessary to couple the return signal in the transition between layers that are not referenced to the same plane. In this case, we are not changing reference planes in the transition between L2 and L1. Could you clarify this for me? Thanks, Maxime

[@Zachariah-Peterson]

I think you're looking at what's going on around 10:43, is that correct? If so, the GND via is more important for the path from L1 (maybe an I/O on a component) down to L2, and it's even more important for the transition from L1 down to L3 or maybe a component on L4. Just routing into L2 you are correct you would have a strong capacitively coupled return path to the GND on L1. There will be a small weakly coupled transition in that top region with the via that could have stronger coupling, and you would provide this with a via. The easiest way to ensure you have this coupling everywhere is with stitching vias that connect the grounds on the top and bottom, and then you just try to route around those or delete any of those stitching vias that interfere with routing.

[@Maxime_Ethier]

@@Zachariah-Peterson Thank you, sir! I was indeed talking about the part at around 10:43 into the video, and now I understand perfectly with these additional explanations. Greatly appreciated! Maxime

[@Maxime_Ethier]

@@Zachariah-Peterson Quick update: I followed your advice, along with some tips I picked up on some Rick Hartley videos, and my 4-layer board works magnificently well. I was able to completely eliminate the EMI that made my microcontroller behave all screwy. Thank you!

[@ytpeep7393]

At 8:50, You mentioned that, as long as you're not routing signals too close in parallel on the two inner signal layers, then this is fine to use. But even if they are routed close in parallel, why would that cause an issue if both signal layers are referencing ground layers much closer than the two signal layers are to each other? The spacing between each signal layer to the ground layer is much lower than spacing between the two inner signal layers due to the thicker core. Wouldn't the much lower impedance between signal and ground nearly eliminate issues of cross talk from signal layer to signal layer?

[@Zachariah-Peterson]

Crosstalk won't be eliminated in that case. The thicker core helps with the distance because greater distance decreases field strength seen by the victim, but both traces have two inductive loops to receive crosstalk, and one of them is large. It actually increases the total equivalent inductance because the two inductive loops can be modeled as being in parallel. So there is still some crosstalk, just hard to generalize if it is a specific amount lower than in the same-layer case.

[@sc0or]

The outer layers are x2 thicker, and are better for gnd/pwr than the internal ones. For me it makes a sense to use gssg stack-up (or s/pgsg if you like) rather than sggs, plus a better shielding and reducing emi

[@oliverer3]

Main problem with that stack up imo is that debugging is a pain and you'll end up with a heck ton of vias which can be problematic.

[@niteendhotre3000]

Hello, I have few questions with 2nd alternative, 1.If our inner layers are GND , do we need to connect them with stitching via? 2. I am working on energy meter board, On top side only display and keys and few smd components present , others on bottom For Power section, analog and digital section I have different grounds Now questions is how do I use inner GND layers with different section Grounding path? And thanks for sharing your knowledge 😊 it will surely help me.

[@Zachariah-Peterson]

1. Yes you should connect them with vias, stitching vias are fine and will help ensure you have a lower inductance return path if you will be making many layer transitions. 2. What is your justification for splitting into digital and analog ground sections?

[@DiegoColl44]

thanks for the info..!!

[@abdelkareemsalem8697]

Great❤

[@inovastar]

Idéia boa...transformadores Slim com trilhas de placas e chapa de metalloy 80 (3)!!

[@WinChester_Ltd]

Hi, Zach. How can I provide a return path using SIG/PWR/GND/SIG, it is seems like there is no option. I can't route on one layer cause there's a lot of signals. Maybe i should use (SIG/GND)/PWR/GND/SIG. What do you think about it? Otherwise it affects on diff pairs😢

[@Zachariah-Peterson]

The first question you should ask is: why do you think you need a dedicated layer for power? Is it because you have high current in the design, or do you have so many power rails that it will be difficult to route them all? Many designers who use SIG/PWR/GND/SIG do so without answering this question first. If you need to route digital signals on both sides of the board then you should use SIG+PWR/GND/GND/SIG+PWR. You could use (SIG/GND)/PWR/GND/SIG for high-speed on both sides of the board but it works best if you only route over uniform power regions with no splits, otherwise you can still create radiated emissions.

[@WinChester_Ltd]

@@Zachariah-Peterson thanks for the reply

[@setia2258]

For better power distribution, should we use a pour or a trace on the bottom or top layer?

[@Zachariah-Peterson]

If by "better power distribution" you mean lower temperature rise when current is flowing, you can use large pour for power if the current will be high. If the current is low, you can just use traces to route power, you do not need large pours if the current is only a few Amps.

[@setia2258]

​@@Zachariah-Peterson Thank you for your reply. I appreciate it. One question: when you said 'a few Amps,' did you mean under 10 A or 5 A?

[@Zachariah-Peterson]

@@setia2258 Under 5 A. Eric Bogatin has a good rule of thumb, a 100 mil wide trace can easily handle a 10 A DC current.

[@DeadCatX2]

The power routing should be copper pours. Maximizing copper pours on signal planes with an alternating polarity from the associated reference plane will increase interplane capacitance, which is usually the only way to fight emissions over several hundred MHz when you aren't already doing something "wrong" (e.g. crossing a split plane). It also makes the copper layers more balanced for manufacturing, but this is less of a concern these days. And it should be solid copper (not hatched) if the intent is to maximize capacitance and minimize inductance. I would also consider switching layers 3/4 of the second alternative as a variant (that is, SIG/PWR : GND : PWR : SIG/GND); the key is to ensure that the pours have the alternate polarity from the reference plane, otherwise there is no capacitive coupling between the layers. This would give you a bit extra interplane capacitance between 2/3, though it's not as much because the outer cores are closer together (like 1/4 the distance in a typical stackup). Stitching the pours together will be easier with a solid plane somewhere in the stackup. Signals from the bottom layer can return through the power pin of the IC, skipping a few vias and a cap's worth of inductance in the process.

[@Zachariah-Peterson]

Wide traces can be good enough for power routing, just depends on the current being delivered. But yes I general I'd agree that you usually get the lowest inductance power regulator layout when you use pour, and it's usually easiest to get power out there to odd locations where a typical trace wouldn't fit if you just draw out a polygon. The copper pour thing is one of those ones where I've gotten into friendly debates. Lee Ritchey has stated specifically that he uses copper pour to increase interplane capacitance in the way you describe. It also provides great shielding as long as it has enough ground vias, which I brought up in another video from the RF perspective. Most new designers though, they just fill in everywhere with copper and ground it at a couple points, then they wonder why it doesn't work so well at those mid-to-high frequencies. Or they will think "I just need to throw copper pour everywhere and now I'll never have an EMI problem", which is also untrue. So yeah, definitely stitch pours together like that if that is how you're going to use them. For the alternate you mentioned, you're already hitting the points I was going to go over tomorrow when we talk about plane capacitance! So yes you would get some extra capacitance, but in the typical 4-layer stackup with a thick core I think it's only fF/sq. in. of capacitance, but it's great for providing some extra decoupling at very high frequencies.

[@kevingai370]

No u r wrong fellow. The best 4 layer stack is Top(sig&component)-Internal Layer1(GND)-Internal Layer2(VCC)-Bot(sig&component). Bcz the internal layer Pair forms an ideal plane parallel capacitor which supply u perfet fast power response. And one more thing, the pwr&GND pair absorb high freq EMIs.

[@thorn9717]

This is an acceptable stackup, and the internal layer will only be a significant cap if the two inner layers are very close to each other.

[@robertbox5399]

Yes. Inner layers tend to be far apart so the capacitance is NOT ideal. Tracks on the surface near the power plane need to be referredto that, not GND.

[@Zachariah-Peterson]

Hi Kevin, Thanks for watching! Hopefully you noticed that I stated in the video that these different stackups all have different uses. Sometimes, the SIG/PWR/GND/SIG arrangement is best, sometimes the alternatives are best. It just depends what you need to do with your routing and layout. The point of showing the alternative stackups was to point out that it can be difficult to provide a clear return path for high speed signals when you use the SIG/PWR/GND/SIG arrangement, depending on the number of digital signals and their edge rate. All of these can be good in different situations.

[@Lu-ql5tj]

That does not work if you have diferencial impedance matching signals in lower signal layer.

[@robertbox5399]

It seems the stackup depends on component density and double sided placement. Lots of vias can cause big issues with gnd plane integrity. Hence you up the layer count with dense boards.

[@romanleduc6007]

I've heard that prepreg layers are not recommended for high speed impedance control compared to core, if you have sig/Prepreg/gnd . At which point is this true / good to consider ?

[@Zachariah-Peterson]

Hi Roman, The difference might be in the copper roughness, not necessarily in the material system that makes up the prepreg vs. core layer. They are different, and the prepreg could be rougher, but I'm hesitant to make a general statement about every prepreg. Yes it is a good point to consider in high speed designs where you might have a long link that has a lot of losses.