Vias and Their Aspect Ratios | PCB Routing

[@hitman74001]

Thank you for all the advanced tips, they have huge impact on pcb designers. Really appreciated.

[@leeslevin7602]

Brilliant, thank you. Looking forward to the video on BGA's.

[@lytvynskyy]

What about covering vias? How reliability differ in tented vs not tented vias?

[@Zachariah-Peterson]

Hi Lyubomyr, I'm working on an article now about this subject. I'll post the link once it's published.

[@sajibislam1677]

Excellent explanation!

[@electgpl]

Excellent! Thanks!

[@victordatdo9880]

If you have time please help me one question about "Power handling in Power divider" Thank you

[@Zachariah-Peterson]

Please find me on linked in and send me your question

[@stanleya.4042]

D is finished hole or drilled hole?

[@Zachariah-Peterson]

Usually drilled hole diameter if you ask a manufacturer. Be careful because some design guides do not distinguish between drilled or finished hole size. As you can see I'm guitly of that sometimes!

[@azizzkkk]

What do you mean like most people work in the imperial system 🙄

[@Zachariah-Peterson]

Or don't, I it's your unit setting in your PCB software

[@maf8801]

How to determine the vía spacing in order to improve the current density and heat dissipation ¿

[@Zachariah-Peterson]

Good question! Unfortunately I am not aware of any IPC standard that might address this specific aspect of PCB design. There are other aspects like trace width sizing which are specified and are supported by data which can be used to create a design, but I have never seen such data or formulas for vias needed to reach a specific current density and control temperature rise. When there is a lack of this data, often a DC field solver will be needed. CST would be a good option for this.

[@GHANSHYAMYADAV-zp9si]

explaining speed is very fast speed.