Decoupling Capacitor Placement and High-Speed Design

[@BillySugger1965]

Hey Zach, I go rather further than you suggest here. Many layout guys have no idea how fast an IC is switching (remember it’s about edge speed, not just clock frequency) and need simple rules to follow. A high speed solution will always work in a low speed circuit, so I always advise the high speed solution. In my world, decoupling caps are _always_ placed on the IC side of the board to avoid vias and minimise impedance between the cap and the IC, and power routed from the via to the cap, then by the shortest possible path to the IC. Never is the via placed between cap and IC. It’s less about power dips and more about minimising high frequency loop area and avoiding high frequency voltage noise on the IC power then being propagated by every connected signal trace. I _do_ agree that BGAs are a problem for this scheme, and that practicality suggests that in these cases caps must be placed on the back of the board. This is a necessary performance compromise, and is part of the reason why ICs in BGA packages have so many power pins. Incidentally, another pet hate of mine is setting aside the decoupling caps in a separate block. I _always_ try to show each cap in the schematic as decoupling a specific pair of supply pins, making it clear to the layout guy what each cap is for, and not just using them as PCB seasoning.

[@harishrao2952]

Hey Zach, may be in the next part you can explain with a specific example about how many decoupling caps are needed for a particular application with some calculations.

[@Zachariah-Peterson]

Hey Harish, yeah I was just thinking about that and how Heidi Barnes was talking about using the inductive slope in PDN impedance to determine capacitance, it's a really good topic. We'll plan on putting something together!

[@AngryMosfet]

@@Zachariah-Peterson I would be very excited to see a video on that topic! Thank you, Zach!

[@kamelk8027]

@@Zachariah-Peterson Hello sir, if you can make a video about that topic, it would be helpful, thank you for sharing your knowledge

[@JohnScherer]

I was going to ask this very question. Can’t wait for the video.

[@thebfam9397]

Looking forward for this too

[@andax2007]

Placement is very important to lower the inductance, but also the decoupling capacitor sizes. With smaller sizes it is often easier to get closer and lower the loop inductance, and the packages themselves too often has slightly lower inductance. Try to avoid using shared visa unless the capacitors are on opposite sides of the PCB (upper/lower). Also don’t underestimate the benefit of plane capacitance between power/ground planes for lowering the impedance for very high frequencies.

[@kayitbilgileri]

Hi Andreas, what is actually mean shared vias? Thank you!

[@BillySugger1965]

This is a rare occasion where I disagree with Zach; putting caps on the opposite face of the board and connecting to ICs using vias is a terrible idea from an impedance standpoint. I _always_ recommend putting caps on the same face as the IC, as close as possible, and routing power to the cap from the via, then from cap to the IC. Remember it’s all about edge speed, not clock frequency, and many ICs briefly shoot through when switching outputs and can take huge pulses of current. Those transient currents need to be sourced from low impedances with minimal loop areas to avoid radiating.

[@Rotwold]

Hello Zack! I would really like to see you cover the basics of crystal oscillator circuit design and layout in a future video. It would be great to know what issues you may face and how to best avoid common mistakes in your design. There isn't a lot of sources online that cover placement and grounding techniques for multilayer boards. The ones I can find either come from forum posts on specific questions, or manufacturers design guides, which often differs depending on the company publishing it. Sometimes they even contradict each other, making it difficult to decide what advice it is you should follow. If you know of any resources on the topic you'd recommend, I'd be grateful to hear about them. Thanks for the awesome lectures!

[@kayitbilgileri]

Altium and Zach, Thank you for these great videos.

[@adambury2251]

Dziękuję ...fajna dynamika prowadzenia wykładu :)

[@AltiumAcademy]

Thank you!

[@joedesimone1444]

Good video. However you did not mention if in your example design, blind or buried via's were used to make the connections to the IO pins from the de-cup caps. BGA's inherently make for very tight trace spacing's under the chip itself leaving little room for through-hole via's.

[@Zachariah-Peterson]

That example is 1 mm pitch with through-holes in a dog bone fanout

[@Zachariah-Peterson]

At smaller pitch eventually it goes to via-in-pad and probably smaller case size to get those caps on the back side of the BGA.

[@hassanrabbaniboyka]

@@Zachariah-Peterson Hi Zach. Why dont you create a course with BGA, DDR routing and explain these in details. Also make a project based course that will be alot of helpful

[@Zachariah-Peterson]

​ @Hassan Rabbani You're not the first person to ask for this, so I suppose I should put this together! I was thinking one about BGAs, routing the main high speed interfaces like DDR, USB, LVDS, PCIe, and Ethernet.

[@hassanrabbaniboyka]

@@Zachariah-Peterson thank you very much.

[@saucebosspl]

Hey Zach, on a 4 layer, the mixed-signal board is it better to use decoupling on the top layer, or the bottom through vias? Packages are SSOP and similar.

[@Zachariah-Peterson]

How is power routed? Are you doing PWR+SIG on the top layer or do you have a dedicated layer for power.

[@petersage5157]

Haven't we already deja'd this vu? Is there a glitch in the Matrix? I could have sworn I'd seen this video much longer ago than May. There are ap notes from TI and Analog saying the same thing for high-speed op amps dating back to the Dawn of the Internet, and a squiz at any old PC motherboard will show that most layout designers were placing bypass caps right at the power pins for logic chips back into the early 1980s. You'll occasionally find one soldered directly *on* the power and ground pins of a chip, and not as a bodge! So this isn't exactly a new development. I specifically remember reading in one of these ap notes (which, rather inconveniently, I can't find atm - I prefer to be able to cite my sources) that some applications could benefit from a little extra inductance and/or resistance in the feed from the power bus to the bypass capacitor, producing a local pi filter.

[@hendor79]

I'd be interested in ways to reflect this in design rules. Anything planned in this regard?

[@Zachariah-Peterson]

Oh this is a really good idea, let me see if there is something I can do with the rooms feature. I hate rooms in Altium Designer, but they are very useful with BGAs, maybe can do something with rooms and component classes to set a room requirement.

[@WinChester_Ltd]

Hi Zach, what is high speed and high frequency signals, I mean, if we're talking about numbers?

[@Zachariah-Peterson]

High speed refers to the edge rate, high frequency refers to the frequency (or the carrier frequency for a wideband signal like a pulse). There is no specific number, but I suppose a good definition for digital signals is that a signal is high speed whenever is propagation distance during the rise time is short compared to the length of the trace or the size of the PCB. For harmonic signals (RF signals) you would use the wavelength.

[@WinChester_Ltd]

@@Zachariah-Peterson thanks

[@sijo2084]

Why 0.1uF cap is always used as decoupling capacitors?

[@Zachariah-Peterson]

The myth about decoupling capacitors is that there are three values required for every digital IC (2 decoupling caps, 1 bypass). The 100 nF cap is basically the larger decoupling cap. For a low current draw, moderate edge rate, and higher core voltages (like 3.3 V or 5 V), this was okay because these systems did not need low PDN impedance. For example, slower digital ICs can work fine with a single decoupling capacitor to provide stable power. Slower digital ICs with many I/Os may need more capacitors because they tend to have slightly faster edge rate and they need to source more current from the PDN in the PCB. This is one reason that you see the recommendation with the 3 capacitors, of which one of these will usually be a 100 nF cap. The reason you see older recommendations for 3 decoupling capacitors is because their impedances sum up to give a reasonably low impedance spectrum across a broad frequency range. This is the characteristic you would like from your PDN and as long as the impedance curve is below some target, then your circuit will operate with minimal ripple. I’ll do a video on this because it is a really good topic for designers to understand in high-speed design, and we have not addressed the 3 capacitor myth directly. To learn more about PDN impedance you can watch this video: kzbin.info/www/bejne/jmWlk2qEoMp3Y8k

[@parasshukla3963]

why not single cap of one value 10 uF rather than 10 caps of 1 uf, that will also not add trace impedances ?

[@Zachariah-Peterson]

A 10 uF capacitor starts to resonate at a lower frequency than the 1 uF cap. If you put multiple caps in parallel, the total capacitance increases, which decreases PDN impedance, but the self-resonant frequency does not change. This is how we add up big groups of capacitors to bring the complete PDN impedance curve below some target up to about 1 GHz. If you are using a component that requires multiple decoupling capacitors in parallel, then it probably comes in a BGA package, in which case you can usually use caps on the back side of the PCB so that the traces are rather small and very low inductance, the dominant factor in the inductance is the capacitor's lead inductance (ESL value) and the via inductance to the plane layers. If you use via in pad on those BGA packages, then you minimize the inductance to about 1 nH per capacitor anyways.

[@parasshukla3963]

@@Zachariah-Peterson thanks for detail explanation

[@ElectricNimPedalsPhilippines]

I learned this the hardway. Lol

[@hassanrabbaniboyka]

Hi Zach. Why dont you create a course with BGA, DDR routing and explain these in details. Also make a project based course that will be alot of helpful

[@Zachariah-Peterson]

We have something coming out shortly with an nRF52 microcontroller, it will show the basic layout with some connectors and explain placement/routing of the antenna.

[@hassanrabbaniboyka]

@@Zachariah-Peterson excellent . I am waiting and excited. Thanks

[@JohnJTraston]

Oh man... this is really wrong. 1. It is not very common to have Vdd and Vss close to each other. In fact, with DIP packages they are on the opposite side. So where do you put your cap? Not a single word. 2. Vias? The back side? That out of the gate reduces efficiency on those caps by 40-60%. Nobody in their mind would do that.

[@Zachariah-Peterson]

Well we can debate how common or uncommon something is if you want since, but fact is I have shown examples in other videos where the pins are close enough to each other to either bridge them directly on the same layer (no vias), or for example on the backside of a BGA using via-in-pad (because you don't have any other choice). Out of the nearly 1500 comments I've answered over the years, yours is the first to offer a counter example with DIP packages! In any case I've discussed the effects of vias on capacitor performance in many other videos. Order of magnitude inductance contribution for a via pair is 1 nH, so for a 0.1 uF decap the SRF will be 16 MHz. No vias and you can expect higher SRF which depends on the lead geometry. That also doesn't include traces. If you have to put caps on the back side then put them on the back side, sometimes you have to do that 🤷‍♂. Take a look at just about any product with a large BGA and you will see decaps/bypass caps on the back side with vias to reduce spreading inductance in the plane layer.

[@rkriisk]

It shouldnt be a problem with DIP packages as they usually contain components which are either slow or not high current. Location of pins though important is much less important than fast DV/DT modern IC's. Have a dedicated GND reference plane and place cap next to vdd pin. Where is your source for efficiency loss ? Caps capacitance is not an issue with decoupling however ESL is and you lose it to via always as you always have GND via no matter what. If you design your board without multiple GND planes then we have nothing to talk about because either your design doesnt need it and you are already fine or you want to design certain circuit in way that is impossible. Same goes for track to power pin as you still get some inductance there and sometimes a lot when fanout from BGA have to use some fine 2-5 mil tracks. As far as I know you don't lose in real life anything when you have opposite under BGA decoupling caps. This 40-60 % is not correct in real life and I challenge you to prove me wrong with actual test data and not some fancy SPICE simulation or worse of some hearsay.