Pretty challenging to find the exact explanation of latch-up problems. This video is amazing and explains exactly what you need to know about latch-up with BJT basics. Thanks a lot!
@hrithiksingla57095 күн бұрын
agreeed. only an old nptel video comes close
@gundloo Жыл бұрын
Great job of explaining an involved concept of latch-up.
@sunnygupta64384 жыл бұрын
Thanks to you sir 👍 they way of explaining of the topic is great .
@gonchar803 жыл бұрын
It's awesome explanation, the BEST i've had hear
@mounikayadav96854 жыл бұрын
Sir please explain about finfet... Your explanation is very well....
@arun653945 жыл бұрын
Thanks a lot sir. It is really helpful to understand the impact of Beta value.
@analoglayoutdesign23425 жыл бұрын
Should you have other questions, please post it in the comments section..thanks
@arun653944 жыл бұрын
Hello sir, Can you pls explain about how guard ring will reduce resistance and how can we say that all are in parallel connection?
@analoglayoutdesign23424 жыл бұрын
@@arun65394 ...sure..I will upload one more video to explain prevention of latch up..I will explain in detail..
@arun653944 жыл бұрын
@@analoglayoutdesign2342 Thanks a lot sir...
@analoglayoutdesign23424 жыл бұрын
I have uploaded a video on latchup prevention. Please go thru. Let me know if further details are required.
@eswareswar15383 жыл бұрын
It's awesome explanation sir , Thanks alot .
@analoglayoutdesign23423 жыл бұрын
Thanks for the feedback
@nikkiscars42223 жыл бұрын
Latch up occurs on pad connected devices due to ESD . Please add this point too
@randomsstudioo6 ай бұрын
great explanation
@analoglayoutdesign23426 ай бұрын
Thanks for the feedback
@chandanasudunagunta82307 ай бұрын
Sir very understandable explanation, y only latch up occurs in final stage of drivers only, please clarify. Thank you
@analoglayoutdesign23427 ай бұрын
Hi.. it’s explained in the video only.. where you have big transistors NMOS and pmos, the parasitic npn and pnp transistors form.. otherwise, for every small inverter, there would be latch up and cmos process could not be used at all..
@digambarbhole9467 Жыл бұрын
sir , @ 14:14 how the substrate taps(i.e gaurd ring) is reducing R1 and R2 can you please explain??
@analoglayoutdesign2342 Жыл бұрын
Hi, please listen to the video again.. bcos when you put substrate taps, the resistance to the bulk connection reduces
@ramadevikothapalli87433 жыл бұрын
Nice explanation sir Pls do more vedios on several topics of layout and lower nodes sir
@analoglayoutdesign23423 жыл бұрын
Sure..will.do..thanks for feedback
@anilsn82194 жыл бұрын
Hi Sir, if there is a power bounce there is a good chance that it will affect other circuits also, how do we take care of this?
@analoglayoutdesign23424 жыл бұрын
if its digital ckt, noise margins will anyway be there...but if analog ckts are connected, we need to take care...please watch Agnd,DGnd & isolation video
@vimakuma6 ай бұрын
Whenever I get rejected in any interview and can't explain how the latch up works. I just come here and revise my basic 😭😭😭
@analoglayoutdesign23426 ай бұрын
Always be prepared.. if you understand the concept, no need to prepare again and again
@vnnmichael8 ай бұрын
Sir how reducing the Resistance is preventing the forward bias of the BJT Transistors ?
@analoglayoutdesign23428 ай бұрын
Vbe is voltage across base emitter.. we have resistance in parallel to it.. that is, if a current flows thru the resistor, it will create a voltage drop across it, which is nothing but voltage, vbe.. if resistance is less, then voltage drop is less or vbe is less and base emitter junction is not forward biased.. hope this answers
@varunde954 жыл бұрын
sir make videos on all failure mechanisms including wpe sti lod antenna em and ir and thank you for this video.
@analoglayoutdesign23424 жыл бұрын
Hi Varun, I have now uploaded WPE video. Please go thru. hopefully its informative.
@varunde954 жыл бұрын
@@analoglayoutdesign2342 tysm sir
@SM-ob5sm2 жыл бұрын
best explanation
@analoglayoutdesign23422 жыл бұрын
Thanks for the feedback
@meghachandargi68053 жыл бұрын
Thank u sir
@ranjitneelakandan95513 жыл бұрын
One question, the 1.8 and 3.3 V that are used do they come from a bandgap source ?
@analoglayoutdesign23423 жыл бұрын
Are you referring to level shifters? If yes, then 1.8v is core supply and 3.3v is I/O supply. Bandgap references cant drive level shifters
@ranjitneelakandan95513 жыл бұрын
@@analoglayoutdesign2342 So as I understand Band gap is used for accurate voltage reference like in ADC etc.
@ranjitneelakandan95513 жыл бұрын
@@analoglayoutdesign2342 Thank you for your reply.My background is more in signal processing algorithm design but taken a keen interest in Analog design.Do you have any plans to use open source tools like skywater pdk along with layout tool like Magic.It would interesting to design the concepts discussed like current mirrors,etc. Thank you again, I learnt a lot from this.
@analoglayoutdesign23423 жыл бұрын
True..that's correct
@analoglayoutdesign23423 жыл бұрын
Ok..got your background. Yes I have done that in the past. But I generally give introduction to topics here in this channel.. Don't take it to design level using free tools.. Should you need more info please email me jt.analog@gmail.com Regards..Jay.
@rakeshyerragopu12983 жыл бұрын
AT 7:41 in Feedback LOOP one direction of current is wrong, I guess Ic of PNP should be upwards
@leviwow7741Ай бұрын
No, it's not wrong.
@SudhirSingh-yb2de3 жыл бұрын
sir, how will be initial base to emitter voltage of npn transistor is greater than 0.7v
@analoglayoutdesign23423 жыл бұрын
Didn't get your question. Can you please reframe and elaborate it.
@rakeshyerragopu12983 жыл бұрын
Suppose, noise
@kshitij88104 жыл бұрын
Sir can you please explain how do well tap cells prevent latchup?
@analoglayoutdesign23424 жыл бұрын
Please watch another video "latchup prevention" everything is clearly explained
@microsoftmath3 жыл бұрын
I THINK 0.7 v is when the impurity is germanium
@M7hero8 ай бұрын
You have wrong connection in the nMOS device, the terminal of the npn should be connected to the drain of the nMOS and not the source.