what is time borrowing (latch) ? why does latches support it?

[@punitjain8746]

I think this also depends on the contamination delay of the combinational circuit? Suppose, we had a positive level triggered latch (as in first example), that the data takes 12ns to reach, clock edge has already passed by then. You swap that FF in exchange for a latch, but if the contamination delay (min time from data injection at input to the time that the output of the combinational circuit starts changing) of the combinational circuit is lower than 5ns, the data will get corrupted.

[@KarthikVippala]

Yes,the examples were taken for explaining , combinational circuit is way complex than shown

[@sarelapini]

Thank you for the interesting video! Why don't you use FF2 with inverted clock instead of the latch?

[@manupotisreenivasulu401]

Thank you very much sir, for sharing your experience.

[@KarthikVippala]

Thank you for your feedback , need any topic , please feel free to comment if I know the topic I will make a video on it 👍

[@neevarpgp]

Whats the point of having the negative latch at all? As long as comb A and comb B are able to resolve the output within one clock cycle, do we need the neg latch at all?

[@KarthikVippala]

Hey Praveen , thanks for asking the question, Yes negative latch is not required if combo A and B can resolve it in one cycle, if not possible then only we use negative latch. Good luck 👍

[@shravan8848]

awesome content

[@coastalfly5508]

Thanks a lottt sir.. Really a nice video 👍

[@KarthikVippala]

Thanks for feedback 😊👍

[@kulayivineeth4931]

what if in the example explained.. instead of negative level Latch, there was a positive level Latch? Is this design possible or it is not practical?

[@ajaykodipelli8617]

Hi sir Can you make a video on SETUP and HOLD (positive, negative and zero setup and holds) for latch.

[@KarthikVippala]

Hey Ajay thanks for asking, I will make the video but it will take some time. Good luck, good health👍

[@y.v.v.nagendra3420]

Hi Karthik, Thanks for the lucid explanation. Please clarify below doubt: In example of low sensitive latch: Flop-A to Flop-B, available time is T. I.e., Delay of Comb-A + Comb-B can be upto T. (In given case Comb-A had > T/2 delay and Comb-B had < T/2 delay, summing to T) So we can still meet timing between Flop-A and Flop B even without latch? (Please correct if I'm missing something)

[@KarthikVippala]

Yep you are correct , I have taken that example to explain that scenario. It might be helpful in understanding certain design. Thanks for asking the question, good luck 👍

[@anushaseerapu8683]

I think using latch we can reduce the number of cycles compared to filp flop.

[@matamvishalakshi1954]

In real-time flip-flops are implemented using transmission gates or NAND gates

[@KarthikVippala]

Namaste vishalakshi 🙏,Based on requirements we choose there is no strict restrictions , but in end there are transistors , Good luck & great health 👍😊

[@aakashek8526]

Sir im having a doubt Then y cant we place latches everywhere? Instead of FF

[@KarthikVippala]

Hey Aakash, thanks for asking the question. Latches cannot be controlled easily as of FF . They are level triggered , are prone to glitches which are unwanted in the design and that is why Flip flops are preferred. Flip flops are Edge triggered which means the change will only occur at the triggering edge of the clock pulse . Hope this clears your doubt,if you have any questions please feel free to comment,I am happy to help you 👍. Please do subscribe it will help me a lot 👍

[@saintenlewis7861]

@@KarthikVippala FF's are prone to glitches right, due to this we are using latches inside ICG's. Correct me if am wrong

[@saintenlewis7861]

Awesome explanation 👌🏻

[@sayanbanerjee4971]

Can you exlain no hold violation using positive latch also

[@KarthikVippala]

Hey sayan , thanks for asking the question , can you please elaborate a bit 👍

[@anushaseerapu8683]

Insted of using latch in this can we define a multicycle path between ff1 to ff2 ???? Could you please answer it

[@KarthikVippala]

But clock cycles will be more questions than n multi cycle path

[@saintenlewis7861]

Subscribing to ur channel after seeing this awesome explanation. Could you please make a video asynchronous data capture between FF to FF

[@KarthikVippala]

Namaskaram 🙏, Thanks for the support and love , good luck and great health😊

[@manupotisreenivasulu401]

Please make the video on the the data checks and Non sequential checks sir,,,,,,,, am little bit confused those topics.

[@KarthikVippala]

Can you please elaborate a bit about topics

[@manupotisreenivasulu401]

Data to data checks

[@KarthikVippala]

@@manupotisreenivasulu401 give me few days , I will be ready with the video , data to data checks

[@manupotisreenivasulu401]

Thank you very much sir

[@sandeeppadma1676]

Could you make a video on TIME STEALING also?

[@KarthikVippala]

Namaskaram _/\_ Sandeep Padma, thanks for asking , it is similar too the video , please go through the topic and feel to ask doubts, good luck & great health :)

[@sunsetgamingyt9077]

@@KarthikVippala thanks 😊. Could you share any article about time stealing, i saw few on internet but I can't understand them

[@kunalsheth2098]

I understand that time borrowing wont affect hold timing but how is time borrowing helpful in resolving setup violation in conjugated region ?

[@tausid979]

Hi Karthik.......Can you please make a vidio on CAM(CONTENT ADDRESSABLE MEMORY) , actually u taught async fifo very easy way so i code it in verilog and its working fine thanks a lot

[@KarthikVippala]

Ok I will check that out, please give me sometime 🙋 , thanks for asking

[@KarthikVippala]

Hey tausid , please tell me what are your requirements in CAM video

[@tausid979]

@@KarthikVippala Ya sure karthik..but please make it possible by friday or saturday

[@tausid979]

@@KarthikVippala We need the same kind of architecture design like you taught us for async_fifo very well , i mean the actual flow of the architecture so that we can code it by using verilog and sv

[@tausid979]

@@KarthikVippala thanks a lot for your quick reply karthik

[@poojakevat556]

Your handwriting 😍

[@KarthikVippala]

Namaskaram pooja kevat🙏, thanks for the support, good luck & great health 👍😊

[@poojakevat556]

@@KarthikVippala same to you. I have my final project submission for VLSI and I found this! I am jealous of handwriting though! Mine is not that good

[@KarthikVippala]

@@poojakevat556 🙏

[@bhanusashankreddy5013]

Can u answer me a question? is Asynchronous counter.....Synchronous sequential circuit??? No one ever answered me this question.......

[@KarthikVippala]

Pls comment the question I will see weather I can do it or not 👍

[@bhanusashankreddy5013]

Can u answer?

[@KarthikVippala]

What's the question?

[@bhanusashankreddy5013]

is asynchronous counter.....synchronous sequential circuit?

[@KarthikVippala]

@@bhanusashankreddy5013 what's ....

[@nephewniece3312]

Is this done only eco stage!!?

[@KarthikVippala]

Yup , you are correct , thanks for asking questions, Sandeep 👍

[@punitjain8746]

what does eco stage mean? (Engineering Change Order?)

[@KarthikVippala]

Engineering Change Order or ECO is the process of inserting logic directly into the gate level netlist corresponding to a change that occurs in the rtl due to design error fixes or a change request from the customer. ECO is preferred as they save time and money in comparison to a full chip re-spin. Thanks for asking, good luck good health 👍😊

[@vnnmichael]

Sir please i have a doubt. in Case #1 , the total time between FF1 and FF1 is 2T . But in case2 , the total time between FF1 and FF2 is only 1T ?

[@KavitaSharma-wm7wq]

Plz sir make video on Clock domain crossing

[@KarthikVippala]

Hey Kavita , thanks for asking I have already made video on CDC based on FIFO and others, pls check it out in synchronizers playlist of my channel 👍

[@KavitaSharma-wm7wq]

@@KarthikVippala okay sir thanks for the reply..

[@anil4128]

i have doubt , why u are using latch with negative level sensitive, because you are saying that the sum of both the combinational delay blocks is equal clock period then the whole computation can be done within the clock period and can available before the clock edge right ?,

[@krustkreeper]

completely confused by the neg triggered latch example. Not sure how you explain time borrowing from this example if you can simply remove the latch?

[@nileshbaldaniya9419]

👌👌👌👌👌👌👌👌

[@KarthikVippala]

Thank you🙏😊

[@abhishektalukdar8471]

You names the edges and the combinational block as A and B. Its soo confusing.

[@zahidahmed3312]

I don't understand the point of hurrying through the lecture ...🥺

[@KarthikVippala]

can you pls watch it at .5 speed👍

[@zahidahmed3312]

@@KarthikVippala Yeah I guess I have that as a last resort

[@KarthikVippala]

Thanks for understanding 👍

[@vengaipuli]

negative latch example is something seriously wrong

[@KarthikVippala]

Can you explain the wrong part , so that I can correct it

[@KarthikVippala]

Thanks mrityunjay for the description, good luck, good health bro👍

[@vnnmichael]

@@dasgoood2811 hello sir , in case of positive latch the total time between FF1 and FF2 is 2T ? In case of negative latch the total time between FF1 and FF2 is only 1T ? please explain

[@vikineo]

This is wrong, please correct, or delete the video and re-upload since a bunch of my friends are getting confused after seeing this. Say Tcyc 10ns, When you have a pos edge flop launching at zero, and data is going to a pos level latch- the data is captured between 5ns and 10ns and NOT as explained where you are saying it is captured between 10ns to 15ns.

[@KarthikVippala]

Hey vikineo I will look at it and update you , thanks 👍

[@vikineo]

Karthik Vippala thank you. Really appreciate your work here and taking the time to make updates and reply.

[@KarthikVippala]

@@vikineo I can't delete the video , if I found wrong in it I will pin your comment on top so it will be clear for the viewers 👍

[@vikineo]

Karthik Vippala sure thanks

[@KarthikVippala]

Your welcome , please feel free to comment. good luck, good health 👍