Clock Gating Basics | Basics of Clock Gating | Clock Gating Techniques |Integrated Clock Gating(ICG)

[@Electronicspedia]

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[@Electronicspedia]

Glad you liked it. Keep watching and happy learning. 😊

[@rohanyadala9096]

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[@bsrinivasarao8622]

IS IT D LATCH OR D FF , AND WHERE IS THE INPUT FOR D LATCH , U HAVE APPLIED ENABLE AND CLOCLK TO ANOTHER INPUT , THEN HOW TO AND WHERE WE CAN APPLY INPUT????

[@bsrinivasarao8622]

LATCH WILL HAVE INPUT AS CLOCK ?? IS IT CORRECT ?

[@Electronicspedia]

Latch will not have clock pin, it will have enable pin. But we are connecting clock to enable pin.

[@rohan-ei4ju]

How is It a latch if we are giving it a clock ??

[@Electronicspedia]

Here we are using clock as enable condition. Not as an actual clock. The basic difference is that it will sample the D input on the level signal of clk.