Course : Systemverilog Verification 2 : L4.1 : Clocking Blocks in Systemverilog

[@carterlee287]

How to handle for inout port with clocking block?

[@FarhanShaikh-pm8bn]

Hi Sir , I have a question about referencing signals within a clocking block which itself is part of modport . Consider following snippet :: interface mult_if (input logic clk, reset); logic [7:0] a, b; logic [15:0] out; logic en; logic ack; clocking cb @(posedge clk); default input #1 output #2; input out, ack; output a,b, en; endclocking modport TB (clocking cb, input clk, reset); modport RTL (input clk, reset, a,b, en, output out, ack); endinterface Assume ' mult_if ' is instantiated in top_tb and then set in config_db to be fetched via driver and monitor . Within monitor , how should I reference output signals ' a ' / ' b ' / ' en ' Should it be :: vif_intf.TB.cb.a OR vif_intf.cb.a ? I observe only VCS throws an error when using vif_intf.TB.cb.a whereas all the 3 tools are fine with vif_intf.cb.a Thanks in advance .

[@FarhanShaikh-pm8bn]

A small correction :: Within driver , how should I reference output signals ' a ' / ' b ' / ' en '

[@nithin_in_ireland]

Clearly explained..thanks

[@SystemverilogAcademy]

Thanks for the feedback :)

[@tahirsengine]

Wow, what a video.

[@SystemverilogAcademy]

Thanks :)

[@Oliver-xp5yh]

good content

[@SystemverilogAcademy]

Thanks for the feedback.

[@manojkumarponduru2684]

Could you please change your payment method....and include any upi transaction like phonepe or paytm.....

[@SystemverilogAcademy]

Hi Manoj, Payment service is completely managed by KZbin, we have no control over that. We are working on adding these courses to our website and accepting payment there, but definitely it will take few months of time.

[@manojkumarponduru2684]

@@SystemverilogAcademy I entered my card details...but it is not working....not only for me ....but for my friends also

[@muhammadfurqan392]

Speak Slowly Please..

[@SystemverilogAcademy]

Thanks for the feedback.