DECAP Cell | Use of DeCap Cells | Placement of DeCap Cell | Layout of DeCap Cell

[@kshitij8810]

Love the content sir... Thank you..

[@TeamVLSI]

My pleasure @Kshitij

[@manupotisreenivasulu401]

Hai sir, This is cnu. Good explanation sir. I have one question sir, within the std cells we will put the decap cells right, suppose i want to put the decap cells between the block to block ,,,,,, i think those case adding decap cells (pmos and nmos) we get problem right, why because we have only n-well and we don't have the nmos, so those case what i can do?

[@TeamVLSI]

Hi cnu, Can you reframe the question please.

[@saiprasadallamraju2692]

One of the reduction techniques of IR drop is placement of decaps. it takes more area. If area is a constraint. Hence this is one disadvantage.

[@TeamVLSI]

YES, it increases the standard cell area, but this is not significant as we have seen. Try to think another factor too.

[@Kamlesh_Paswan]

Is de-cap part of AMPG verilog netlist generated by APR team? How APR team decides the de-caps values ?

[@TeamVLSI]

Hi @Kamlesh What is AMPG? and could you please re-frame your question.

[@ArunKumar-wu4px]

I have a doubt in placing decap cells..How do we know in particular region more current will draw by STD.cells..bcz before placement if we place decap cells...

[@TeamVLSI]

Yes Arun, initially we place decaps in a regular intervals, It provides a boost to power network. But again after IR Analysis, We can insert decaps in a particular regions.

[@RevolveRider]

Sir according to El Moore's model si->insulator->metal wire already behaves as capacitor and resistance then why can't it help in resolving this issue?

[@TeamVLSI]

Yes, alright! The said combination of materials behaves as a capacitor. But I am not able to understand for which capacitance you are talking about. 2nd fact is we have to see the capacitance too. Is is considerably large or not.

[@RevolveRider]

@@TeamVLSI yes sir i got it, actually I am in first year and in this lockdown I am gaining knowledge about digital electronics as much as I can and also completed vlsi cad course from coursera but I am not getting right path what to do next, should I learn verilog next sir? Or what should I do next please guide me ..

[@FerozAhmed_PhysicalDesign]

I think Decap cells are not only used at pre-place or in power plan stage. it is used at Routing stage as IR drop will be high at this stage.

[@TeamVLSI]

Alright Firoz! I have mentioned that at the end of video 15:56

[@FerozAhmed_PhysicalDesign]

@@TeamVLSI oh yes, In middle of the video I've seen you have mentioned Pre-placement, didn't go till the end, sorry for this 😅 Your videos are very informative, that's for the efforts you've put in.

[@TeamVLSI]

@@FerozAhmed_PhysicalDesign Thanks a lot dear!! Keep supporting.

[@FerozAhmed_PhysicalDesign]

@@TeamVLSI *that's = thanks

[@manojgutha5686]

Hai, if you connect gatepoly directly to vdd, then it will damage right?

[@chandrakanth.m.s.63]

Yes, that's why they have moved to cross coupled Decoupling Capacitor structure I guess (check near this -> 14:23).

[@rajgandhi4042]

Why it will damage? Please explain?

[@shahidafridi90]

Also there will be routing congestion problem, which can be fixed using blockages. But , this results in increasing the Core utilization area.

[@TeamVLSI]

Hi Shahid, I am not able to get your first part of comment: How it will increase the routing congestion? It doesn't requires any additional net to route them as it has no signal/clock pins.

[@shahidafridi90]

​@@TeamVLSI Hi Sir , I mean that as we use the Decap cells for clock buffers while clock routing , it will occupy certain area on the chip. This will decrease the available area in the core for routing other signal nets.Thereby leading to congestion in routing. Kindly let me know if I am wrong

[@TeamVLSI]

@@shahidafridi90 Yes, Increased utilization will affect the clock tree synthesis.

[@srinidhiala3672]

The disadvantages of Dcap cells are 1. Area 2.leakage power..

[@TeamVLSI]

Well said Srinidhi.

[@marun5778]

Hello, May I know how 2.Leakage power happens here.?

[@ChuChu-id8cc]

@@TeamVLSI could you explain more about leakage power here?

[@User--jm5916]

Command to place decap cells?

[@TeamVLSI]

He Radha, Pls do man addDeCap to get all the options of adding decap cell.

[@venkateshchanda1713]

decap cells are more leaky..so more cells more we get leakage problem

[@sweetymits1243]

We added tie cells, even though we need Decap cells answer???

[@TeamVLSI]

Hi Sweety, Tie cells don't tie the well. It is used to tie a net/terminal. Both have different function. Please see the video of tie cells.

[@ArunKumar-wu4px]

Leakage will be more

[@TeamVLSI]

Exactly ...

[@nikitak3605]

@@TeamVLSI can you exPlain why leakage will be more?? we use decaP for ir droP then how come it cause leakage

[@achintize]

Where is antenna cells

[@TeamVLSI]

Thanks @Achint, for reminding me We will add that soon, few more.