Multi cycle path in VLSI | Multi cycle path Constraint | Multi cycle path example

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Team VLSI

Team VLSI

Күн бұрын

Пікірлер: 30
@ArunKumar-wu4px
@ArunKumar-wu4px 4 жыл бұрын
Nice presentation
@TeamVLSI
@TeamVLSI 4 жыл бұрын
Thanks a lot Arun. Keep supporting!
@mekalagowthami162
@mekalagowthami162 10 ай бұрын
Sir.. can you tell... How we will get know about MCP. Is there any command to check what are the MCP in our design..(consider we didn't set MCP in sdc fie)
@nagarajunaani5004
@nagarajunaani5004 4 жыл бұрын
Nice Arun ... Keep continue this series on short topics ... Thanks
@TeamVLSI
@TeamVLSI 4 жыл бұрын
Sure 👍
@omkarrasal9224
@omkarrasal9224 3 жыл бұрын
As you said after applying MCP for setup after 4 clk cycles ,hold will be checked at before that clk cycle But hold will be checked at same Clk edge and that are both different edges pls clarify my doubt
@TeamVLSI
@TeamVLSI 3 жыл бұрын
time stamp please.
@mytravelstories8587
@mytravelstories8587 Жыл бұрын
sir you have written start in the command and making changes in the end clock in the final example please check it. If i am wrong let me know
@omkarrasal9224
@omkarrasal9224 3 жыл бұрын
While writing for MCP for hold you told 3 that Is (n-1) and in note you are telling applying MCP for setup hold gets affected by same no of cycles in Same direction pls correct me if I am wrong
@TeamVLSI
@TeamVLSI 3 жыл бұрын
time stamp pls of video.
@arunsahni3940
@arunsahni3940 3 жыл бұрын
@@TeamVLSI at 15:23
@sonikumari-xf4ls
@sonikumari-xf4ls 4 жыл бұрын
Why setup check is done at next clock edge and hold at the same edge?
@amrutagulgond2265
@amrutagulgond2265 4 жыл бұрын
Setup always affects the capture flop and hold affects the launch flop
@darbylarson8800
@darbylarson8800 4 жыл бұрын
Hold constraint is basically trying to prevent a race condition so that a fast data doesn't accidentally pass through to the capture flop at the same clock edge, so hold check is only relative to a clock edge. Setup constraint is trying to prevent a scenario where data moves so slowly that it doesn't get to the capture flop even before the NEXT clock edge, so it needs to take the entire clock cycle into consideration.
@AmmammaNanammakathalu
@AmmammaNanammakathalu 3 жыл бұрын
If I have a hold violation of 100ps how much setup slack I need.
@TeamVLSI
@TeamVLSI 3 жыл бұрын
Hi Aneel, Generally 2 to 3 times depending on library.
@AmmammaNanammakathalu
@AmmammaNanammakathalu 3 жыл бұрын
@@TeamVLSIHI could you please make a video on why do we need virtual clocks
@KavitaSharma-wm7wq
@KavitaSharma-wm7wq 4 жыл бұрын
can you please check once where will use -start and -end switch? I think in slow to fast we use -end switch and in fast to slow clock we use -start switch....please let me know also if I am wrong
@TeamVLSI
@TeamVLSI 4 жыл бұрын
Thanks, Kavita. You are right. The way you are saying will always shift the check edge with respect to the shorter clock period, Which is absolutely right. But I don't think it is a necessary condition.
@arjunnatukula7128
@arjunnatukula7128 3 жыл бұрын
grt work
@TeamVLSI
@TeamVLSI 3 жыл бұрын
Thanks Arjun. Keep learning keep supporting...
@arjunnatukula7128
@arjunnatukula7128 3 жыл бұрын
@@TeamVLSI bro..can u do for rtl.spec..like coding constraint, linting
@ArunKumar-wu4px
@ArunKumar-wu4px 4 жыл бұрын
How multicycle will help to fix hold time
@TeamVLSI
@TeamVLSI 4 жыл бұрын
Hi Arun, It wont help.
@saijagadeesh1708
@saijagadeesh1708 3 жыл бұрын
Why hold is reverting back after applying MCP?
@TeamVLSI
@TeamVLSI 3 жыл бұрын
Hi Jagdeesh, Because we want to provide MCP only for setup.
@anithasabhavat6064
@anithasabhavat6064 3 жыл бұрын
How to identify multi cycle paths in design?
@TeamVLSI
@TeamVLSI 3 жыл бұрын
It is an exception, you can check the SDC file.
@debmallik
@debmallik 3 жыл бұрын
@@TeamVLSI If it is not there in SDC and then how to identify violation is true or false due to multicycle
@suprajithhs5609
@suprajithhs5609 3 жыл бұрын
Check for flip flops which are driven by clocks of different frequencies.
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