DRAM 05 - General Read and Write Operation on DDR Channel

[@karthikk.v4827]

Great series. Please keep on adding more videos. Thanks!

[@openlogic925]

Thanks for the comment. I'll try my best.

[@ahyungrocks5509]

OMGoodness! This video is easy to follow with great visual aid. Please keep it coming. You have a new subscriber.

[@openlogic925]

Thanks for the comment. I'm currently busy with my job. I'll post new materials as soon as possible.

[@ashtsw]

Love the way you made it easy to understand, we need more videos like this, please explain timing parameter, drift and ck to wck sync with write and read operation. Also, a separate video on command gap.

[@openlogic925]

Thanks for the comment. These videos will come, but they'll take time.

[@geethnadh]

Very well explained LKK 👍🏻😀

[@openlogic925]

Glad you found it helpful!😊

[@chandrasekharsattar5633]

thank you sir , very well explained. Much better than our college 👍

[@openlogic925]

You're welcome. Let me know if there's an opening at your college 😁

[@BitByte2]

Fantastic video! I now understand why accesses to the same row are faster than jumping around. I would imagine that memory requests could be sped-up if reordered such that row accesses change as infrequently as possible. I'm guessing this is what the Xilinx MIG IP "memory command reordering" setting does. Do you know if most DDR controllers support reordering of memory requests? Are there other factors than row addresses that may cause memory commands to be reordered?

[@openlogic925]

Thanks for the comment. I do not know the actual meaning of Xilinx MIG IP "memory command reordering". I feel it is related to cache coherency , not on DDR. There is a concept called bank interleaving, which is how DDR controller minimises jumping on different rows; I believe this is widely implemented.

[@chandrasekharsattar5633]

sir one query , is the write and read leveling is done at start of the dram controller, sir one video on ddr zq calibration and PHY interface along with training, calibration and initialization sequence would us alot sir .

[@openlogic925]

They definitely happen once during initialization. There are calibration which are done periodically, but I'm not sure if write leveling is one of them. Thanks for the support, but to be honest, while I have plan for other videos on DRAM, they will take time.

[@thesunwillshine11]

You creating another channel after using me all these years shows the cruel nature of man 😢

[@openlogic925]

I don't know who you are. And this channel is my own effort.

[@thesunwillshine11]

@@openlogic925 It is enough to say you don't know me after using me and blocking me on discord. Keep it up. Your fall is imminent

[@openlogic925]

@@thesunwillshine11 Funnily enough, I don't know what discord means and have to search it up. Assuming you meant the social app discord, I have never used it. Once again, you got the wrong guy.

[@thesunwillshine11]

@@openlogic925 I got the wrong guy? Okay nah

[@joecox9958]

waveforms are allmost incorrect - clk edge

[@openlogic925]

I'm sorry I don't get it. If you don't mind enlightening me, which part exactly? Clk against cs/ca? I did think about aligning the clk edge to the middle cycle of cs/ca, but then I thought it's not important yet, until I create another video to look deeper. There are other aspects that I chose to "ignore" too for the time being, like the preamble behaviour. But then again, I'm not sure which part you're referring to.