DVD - Lecture 4e: Verilog for Synthesis - revisited

[@Digital_system123]

Hi adam, thanks for your wonderful lecture series.. I am having a doubt at 9:09 in the low power clock gated RTL, you have used a clock signal on RHS of assign statment, as you have earlier Disscued that it should not be done that way.. Can you dicuss more about that?

[@AdiTeman]

Hi Atul, Good observation. Indeed, it would seem that I broke one of the "unbreakable rules". But, as I like to tell the students in my courses, everything I describe as a "ground truth" actually has cases (sometimes very frequent cases), where it doesn't hold. This is a bit of that. When I defined the "law" of "do not put logic on the clock", I probably mentioned something like "unless you really know what you are doing". In this slide, I describe clock gating for low power design. The assign statement here is directly describing clock gating logic. In other words, "we really know what we are doing". In fact, there are many reasons to put logic on the clock, but as a beginning RTL designer, you do not want to do them. As an advanced RTL designer, you would be expected to understand the implications of doing this, and in 95% of the cases, you would understand that you're not supposed to do it. But there is still that 5%, where you understand really well why you want to put logic on the clock and they it will be correct. Regarding this specific case - you will probably never do this exactly. A single flip flop will not be clock gated. You would usually use enable logic (like the first example) and if there are several flops sharing the enable condition, the synthesizer will automatically insert an ICG. An assign, such as in this example, would usually be used on a global clock gating signal. But even then, usually you would instantiate a specific standard cell from the library and not use a synthesized assign.

[@chaitanyakunda8583]

In the 2nd way of clock gating, I am under the impression that this works in ASIC but not in FPGA considering the architecture for clk. Do you have any comments on this, it will be very helpful. Thanks!

[@AdiTeman]

Yes, this is correct. In fact, it's very hard to take most of the things that I discuss that have to do with the clock over to the FPGA field. FPGAs have a pre-designed structure with proprietary CAD tools that map the RTL to the hardware. The clock is pre manufactured. There may be different methods for clock gating and saving power, but the granularity is much lower and for sure, the are not the methods (exactly as) described here.

[@dontevenwasteaday8983]

do we still need to do clock gating setup/hold check if we use latch based ICG? I think we don't since clock gating setup/hold check is for glitch checking while with latch based ICG the glitch is prevented already, please correct me if I am wrong, thank you

[@AdiTeman]

Good question, and interestingly I just answered it for the comment after yours. Yes, we still need this check. The glitch free clock gate makes sure there is no glitch on the clock when a signal is allowed to glitch. The clock gating check makes sure that the signal doesn't transition when it's not allowed to. Looking at the enable signal, it is a combinatorial signal. Therefore, transitions in upstream logic will dissipate down until the enable net and can transition and possibly glitch. This is standard and acceptable behavior of the signal. Two problems can occur: a) the transition (including glitch) occurs too close to the clock edge: this is a setup/hold violation and must be eliminated by design (STA checks and timing optimization) b) a glitch occurs on the clock due to the AND operation of the clock gate: this is what the ICG fixes and you don't need to do anything in regards to STA.

[@ghassanakesh]

Hey Adam, Thanks for these wonderful and helpful videos. I wanted to ask about the Glitch-free Clock Gate, what happens if a glitch in the enable signal occurred at the edge of the clock? (part of the glitch is when the clock is 0 and the other when the clock is at 1)

[@AdiTeman]

Hi, Great question. This, indeed, would be a problem. But the same is true if you catch a glitch on any other path in the design. In fact, this is the objective of Static Timing Analysis - to make sure that the signal is stable before (and after) the relevant clock edge. It may not be that straightforward that this is the same as reg2reg timing, but it's just an extension of it. I didn't go into this in the STA explanation, but in addition to reg2reg, in2reg, reg2out, in2out paths, there are other STA checks that are done. I mentioned "recovery" and "removal", which are check vis-a-vis the reset signal. But an additional one is the "clock gating check". That is exactly what you are showing in your image. It makes sure that the "data" (in this case the "enable" signal) is stable within the setup-hold window around the clock. With a latch, we can easily ensure this, but it exists in similar paths "gated" by an AND gate or other structures. It's just harder to ensure the synchronization with such a combinatorial gate, and here I showed how the ICG is perfect for ensuring the condition.