3 Bit Asynchronous Down Counter | Sequential Logic Circuit | Digital Circuit Design in EXTC

[@turaysamuelm.4445]

Words can't express how much i love your tutorials🙏❤️

[@neerala2424]

Nice Video 👍 mam I cannot understand anywhere 🥰 But your vdo is understood me .... Thanks 🙏 mam.

[@anishrajak693]

The circuit diagram is incorrect Next clock pluse must be given from Q' for a negative edge trigger down counter

[@musarrat1050]

yes

[@ck-hq5iq]

or we shall use possitive egde for if we go with qn

[@thepahadiclasher3926]

Our professor told us to use the complemented output as the clock for 2nd ff and 3rd ff...

[@PhaniManjunath.]

Thank u mam

[@Aashish0049]

As far as I know, the state changes on the positive in the downcounter. 🤔

[@Humordose_op]

Thats not right brother It changes on negative edge only

[@VikcyAnthati]

Super akka

[@VikcyAnthati]

😘

[@muqadasakram6587]

Agr down counter k liye counts krna ho 15 to 0. And clearly show timing diagrams of all the states

[@Molecularphysics12]

But If output Q is connected with negative edge triggering to clk pulse then its down counter

[@priyadarshiroy9584]

Up counter not down

[@queenieluong]

periodddt queen

[@Aashish0049]

State changes on +ve edge trigger or, on -ve edge trigger , in Downcounter

[@rabin2439]

You can change it on any state bro, either positive or negative.

[@yashSharma-fn8fm]

Bhaiyon ye circuit diagram galat bana he

[@muqadasakram6587]

Jaise ap ny yaha py 8 li thi waise he hum 15 ly gy

[@RaviYadav-bj6mw]

diagram is wrong I think

[@udaytavare3814]

Yes diagram is wrong

[@muqadasakram6587]

Hello mam

[@Simran_Kodere]

Wrong diagram

[@sanketkumbhar]

How

[@sanketkumbhar]

Can you explain me please 🤔

[@musarrat1050]

yes

[@shitalghodmare1274]

Because Qbar is given input as a clock

[@ramrajedeshmukh2783]

Yes

[@yashSharma-fn8fm]

Bhaiyon ye circuit diagram galat bana he

[@yashSharma-fn8fm]

Bhaiyon ye circuit diagram galat bana he