3 Bit Asynchronous Up Counter |Sequential Logic Circuit | Digital Circuit Design in EXTC Engineering

[@mondeinnocent2353]

That was the best explanation

[@sooryanshsingh2957]

Crisp clear explanation with neat and clean writing and diagrams.

[@DC-xg4fi]

sahi bola

[@d.akshayrollnum2457]

Thank you for the explanation mam keep it up best ☺️

[@ArikBiswas-ti9dx]

mam why we connect it in logic 1

[@manali7404]

Do we need not to use preset and clear?

[@rshan7375]

Thank you😊😊❤❤

[@Ekeeda]

You're welcome 😊

[@windyzanele3813]

Thank you Mam

[@THEENGINEERSVOLG.]

thank you

[@kumardev]

Great...

[@naziaparveen2787]

Thank u man so clear topic

[@hymareddy2003]

What if we apply logic 0 it will applicable or not

[@nooralam013]

Superb 😊

[@Pratap-r9z]

Tq Sister

[@satejpatil9990]

thanks mam

[@i_am_komal_ok]

Thank you ma'am

[@harishyashwantjadhav705]

Thank you mam✨

[@azadpathan8040]

Thanku mam 👍🏻

[@sangramwabale]

It is Asynchronous down counter.

[@KundanaKamisetty]

Mam can we take +ve edge triggering in time diagram??

[@prachetamitra8574]

Can someone please explain why clock signal is inverted for asynchronous up counter

[@lovelychauhan664]

the only difference is between asynchronous and synchronous is just about clock pulse ...in synchronous will clock signal will give transition to every flip flop but in asynchronous the clock will give only transition to 1st flip flop and the rest will give by the output of previous ff

[@smartsiva2757]

Any notes for this mam