Electronics Interview Questions: FIFO Buffer Depth Calculation - Part2

FIFO depth calculation and basics of clock domain crossing are touched in this tutorial. This video provides a logical way to go through one of the most common hardware interview questions where you are provided with two different clock domain systems and you are required to transfer data between them.
Complete playlist on FIFO interview Quesitons is available here:
• Interview QA: FIFO Dep...
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[@bournsted4512]

Thank you sir for explaining this so simply and elegantly. Got very confused reading this concept from many different sources. But you made it crystal clear and now I think this topic is so easy because of you. Thank you again Sir. Very Helpful. ❤

[@TechnicalBytes]

Thanks for your comments !!

[@idontcare-tk1te]

Great explanation. Clear and to the point!

[@ankitasharma9841]

Can you please create more videos on this topic with increasing complexity.

[@priyasahoo4280]

The one idle clock cycle means exactly similar to no idle clock cycles only right? Because always there will be one clock cycle delay between alternate writes and reads. so why we have multiplied it with 2?

[@TechnicalBytes]

I am calculating time taken to write and read one byte. It will be double of the time period. but you are correct after all the calculations, this scenario is similar to no idle clock cycle scenario.

[@manveersinghmehra]

NICE😊

[@TechnicalBytes]

Thanks 🤗

[@pseudohawk1656]

Explained very clearly. Thanks

[@TechnicalBytes]

Glad it was helpful!

[@sureshk740]

Thanks for the good explanation. What would be the minimum burst to burst gap in these cases? In the case of last example, is the minimum burst to burst gap is (83 * 80ns)?

[@TechnicalBytes]

try to calculate and I will correct you if wrong..

[@sintan4754]

83*80ns =6640ns is the burst gap

[@meenugarg1102]

Good explanation thanks

[@TechnicalBytes]

You are welcome

[@arpittiwari7695]

Can you explain how this synchronizer and FIFO designed? Is the FIFO just an SISO Shift registers?

[@TechnicalBytes]

Arpit, Soon we will start session on clock domain crossing. We will explain the functionality and design of async FIFOs there in great detail.

[@maheswarreddy4394]

no.of idle cycles for read is 3 right, but when you calculate read one data byte how it becomes 4*1/fa? Please clarify me

[@ankushkumaryadav65]

As idle cycle means after reading for one clock cycle then for next 3 cycle no operation ... So it means in 4 cycles it will read one time only ..thats why he had taken 4 in calculation

[@PremKumar-jq3wg]

If here the burst size is not given data read is continuous, how can we calculate FIFO Depth here

[@vinodshet27]

Waiting for more videos..

[@TechnicalBytes]

Sure 😊

[@venkateshrathod393]

I have confusion in question ,you mentioned 1 cycle ideal after two successive reads and writes but u considered for only one successive read and write

[@TechnicalBytes]

Hello Venkatesh, I mean there is a idle cycle after every read. in the same way, there is a idle cycle after every write.

[@venkateshrathod393]

@@TechnicalBytes Tq

[@deepchandmeshineni702]

Time taken for last byte to write is only clock cycle .for the last why you considered as two cycles can u explain ?

[@mpraveen4937]

its just consideration,

[@priyasahoo4280]

sir I have seen questions where data reading is faster and writing is slower but even then also FIFO is used as no of idle cycles were different. need some more clarification on that.

[@TechnicalBytes]

You are right, FIFO may be required even if writing frequency is slower and reading frequency is higher in case number of idle cycles at the time of reading are quite high as compared to number of idle cycles during writing. Remember, actual reading and writing speed is dependent upon frequency as well as number of IDLE cycles. Now, if writing speed is higher than reading speed. you will definitely need a memory buffer/FIFO. let me know if any further clarification required.

[@priyasahoo4280]

Thank you sir !!

[@ratansingh3086]

please create some other video like this ..

[@TechnicalBytes]

Sure .. Ratan ..

[@tejinderkumar4344]

Very nice sir

[@TechnicalBytes]

Thanks and welcome

[@vinaymotupalli]

Is burst size = 100 bytes is correct or burst size = 8bits , burst length = 100 is correct ? while considering burst write into FIFO ? I need some clarification on it please sir make a detailed video with diagram to visualize on fifo data transfer between 2 modules

[@mpraveen4937]

in one cycle it will write one byte. fifo width will be of one byte

[@user-oc9ti3zm2r]

I got this interview question Does anyone have the problem workout and solution ? What is the minimum FIFO size required here Writing Data = 80 DATA arrives in up to 100 Clocks Outgoing Data= 8 DATA is read in up to 10 Clocks Data write/read is done with bursts of 160 DATA The data provided is confusing compared to these simpler problems.

[@TechnicalBytes]

It is not confussing, it is incorrect. Your effective write and read speed is same.

[@TechnicalBytes]

Give me correct data, will solve it