FPGA and BGA PCB Power Delivery Best Practices

[@jimtekkit]

I subbed and was watching videos on your Phil's Lab channel before coming across Altium Academy, and it clicked that you're the same guy. Even though these projects are far beyond my own design capabilities I find that your content is packed with stuff to learn and you do a good job of explaining designs that I otherwise wouldn't have a clue how they work.

[@PhilsLab]

Thank you very much! Very glad to hear that you like the content both here and on my own channel - much more to come! :)

[@EfraAv]

Great video, PCB Power delivery for FPGAs is tricky I'm glad you shared these tips

[@AltiumAcademy]

Glad it was helpful!

[@Niels_Dn]

Love the TagConnect JTAG, I also use those a lot 👍🏼

[@AltiumAcademy]

Right on!

[@robv3872]

Really great video Phil!

[@myetis1990]

Hey Phil , great job, thank you for the practical life saving tips and tricks, nice to see you in the Altium Academy team. It would be amazing if the hi speed ports such as pcie lvds hdmi are explained(both working principle and layout tips and tricks) keep up good work,

[@PhilsLab]

Thanks a lot, Mustafa! Those are great topic ideas for future videos - will definitely aim to make some videos on that, thanks!

[@thomassorensen7907]

Hi, Great video. Question about the the stackup. Why not PWR plane on layer 3? As you mention in the video the tight coupling between a PWR and GND layer is important at higher frequencies and in this way it would be closer to the top signal layer where the FPGA is.

[@joncedarleaf]

Excellent explanation Phill! That was very helpful. Question about the capacitor selection: Are the FPGA capacitor value recommendations in the datasheet based on an example hardware layout, and the frequency response of that particular example PDN's layout? Or do they make some assumptions about what your PDN design will look like in terms of inductance/capacitance values? I thought the various sizes of capacitors in a PDN should be selected to minimize your specific PDN impedance across various frequencies, which is unique to each design.

[@PhilsLab]

Thanks, Jon! That's right - the specific/exact capacitors should be ideally tuned on a case-by-case basis, for high-perfomance designs. Through the datasheets and app notes they've made some simplifications - to my knowledge however not based on a particular example (could be wrong). On another note, I've seen many commercial designs that have gotten away with using less capacitance/capacitors than given in the Xilinx datasheets - not sure how/if they went about PDN simulation though.

[@MrKrishnanandaKHegde]

Great videos 👍.. we are learning a lot from you. Could you please share the layer stack for this board.

[@優さん-n7m]

You have placed a via for supply and another for ground and tried to bring them close. However, why do you need to do this when you are going to connect the capacitor to GND plane and not the actual FPGA ground pin?

[@petergagliano3756]

Hi Phil, great video! I am curious though do you layout the other elements first and then leave your decoupling layout for last or do you do the decoupling first, ie I'm trying to get a better sense of what a good workflow is for this kind of board

[@peteckone]

This was really useful! Thank you Phil. Which manufacturer are you going to use for PCB and assembly for this board?

[@PhilsLab]

Thank you - glad to hear the video was useful! I'm currently having the boards manufactured and assembled by PCBWay.

[@laghssiibtissam6241]

hello, thank you for that, i want to create a pcb includes UB and FPGA and SFP In altuim but i have somme problems

[@Zachariah-Peterson]

We are working on an Ethernet switch project that includes SFP and will record this for an upcoming video, keep watching the channel and you'll see once it is released.

[@milind_jani003]

Hey Phil, it's always fun to watch your videos. I was wondering if the different power planes adjacent to each other on the same layer will cause some problems related to parasitics? Or will there be any problems if we have such voltage planes close to each other as they might form a capacitor? Thanks in advance.

[@hanelyp1]

Is there some specific reason to not overlap pads and vias?

[@tissuepaper9962]

Solder will be wicked into the via, leaving you with a starved/weak solder joint, and possibly even dripping through onto the other side and causing a short somewhere. There are special tips and tricks you should follow for putting a via in a pad, there's another Altium Academy video about it.

[@eggxecution]

nice

[@romanowskis1at]

It is realy disturbing me when i have to watching schematic where chips are unknow package or have not specified it near component designator. Pack/footprint shall be always visible on schematic. People sometimes read and study schematic on paper/pdf. Unprof in many ways.

[@calypso5925]

Like number 100h

[@firashammad5775]

slow down a tad man