Interfacing FPGAs with DDR Memory - Phil's Lab

[@jjcampbell009]

Well done Phil. I appreciate the basis for DDR2 design choice. I am using a similar arrangement for an AI edge accelerator. I am using a bespoke memory and cache controller with my own microcode.

[@bansci]

Wow you really see the value of the professional tools in the integration of the IP/hardware, and the delay matching in Altium is really impressive. I'm still trying to stick with Kicad and project icestorm hardware but i know that means low speed designs or lots of pain!

[@PhilsLab]

Yeah, there are a lot of Altium features I couldn't do without anymore. KiCad is still great (and free) though and would be able to create these kinds of designs, however, it would take me quite a bit longer with some 'roundabout' methods.

[@edvardoblocinski1655]

@@PhilsLab it sucks that Altium has no hobbyist licencing, I can use the licence that work provides me with but I wouldn't be able to design and release products using it as it would mean that whatever is designed, belongs to the company

[@優さん-n7m]

@@edvardoblocinski1655 yes, it does

[@ElectroTurjman]

Great Video ! I'm interested to see you test this board very soon! I also noticed that you have used resin-plugged and capped vias, Is there any reason for that? It really looks fantastic.

[@PhilsLab]

Thank you! I wanted to try out a different manufacturer for Rev B to compare PCB qualities to PCBWay. They offered plugged and capped vias as standard with no surcharge.

[@優さん-n7m]

@@PhilsLab Phil there is a matter that I wanted to highlight. High speed interfaces often use microvias and might need vias with no stub which means blind and buried vias or those that have been back drilled. JLCPCB does not do any of these things. Does this mean that JLCPCB is not at all suitable for manufacturing high speed boards?

[@alancabrera7116]

Interesting. It looks like some label bits of the SPARTAN-7 have been “redacted”. Why is that?

[@PhilsLab]

Just copying the comment from 'd. timber' on a previous FPGA + microcontroller video: "Lot code and QR code are removed so that Xilinx isn't able to trace back the parts to the official distributor. This is done because Xilinx forbids the selling to Europe and USA for Asian distributors by contract. It's likely that these parts were sold to "end customers" which then remove the trace-ability info from the part and then sell those parts to companies like LCSC/JLCPCB"

[@supernumex]

@@PhilsLab Is it much cheaper from lcsc/jlcpcb or was it just easier because you had the board assembled there?

[@PhilsLab]

The AMD/Xilinx parts at LCSC are A LOT cheaper than through the 'usual' distributors. I paid something like 20 USD for a Zynq XC7Z010, instead of 100+ USD.

[@supernumex]

@@PhilsLab oof, that's quite a difference.

[@homemade-it2495]

I've seen in a demonstration of a Norwegian engineer about FPGA that there are some Xilinx ships costs 70,000$ which shocked me 😮😮

[@PATRIK67KALLBACK]

Phil's Lab videos are always so filled of great tips and tricks how to design pcb and schematics. However, sure it would be gret to use Altium Designer but as a DIY hobbyist which of us have the money to pay €460 per month? Well I continue to use KiCAD.

[@asmi06]

One thing to keep in mind is that DDR controller will consume about 20% of this FPGA's resources, and it's the largest density device in this package, so it's a bit of a bummer. This is one of reasons I prefer FTGB196 package when IO count is not an issue - as there is an S50 device in that package, which has double amount fo resources compared to S25. Also whenever I design a DDR2/3 interface, I typically do a layout for the largest capacity supported by the tools, even if I intend to install smaller capacity device, as this will allow me to install larger capacity memory device in the future should I decide to do so, without requiring PCB changes and a respin. The largest capacity device that I managed to cram into a single IO bank is a 256Mx16 (512 MBytes) DDR3L device, for that to work I had to hardwire memory chip select signal to a ground to save one pin for a higher address line (unfortunately MIG does not allow sharing byte lanes used for data with address/control signals).

[@RixtronixLAB]

Nice video, well done, thanks for sharing :)

[@fedimakni1200]

can we see this pcb in action? any project where we can interface with something and see how things work and the its utility, limitation, etc. thank you for the video very helpful

[@PhilsLab]

Check out the previous videos in the description, they show a few aspects of the PCB in action. Next video will be setting up the DDR memory and testing it.

[@MikeHarris1984]

I am copying one thing you did that was an excellent idea. My series of items im designing, im making the proc, storage, memory on an m.2 board too. So the projects can be pretty much the same and i just make a 2Mb one, 4Mb, 8Mb versions and diffrence procs to test with too. Thinking of on the boards for the projecs, the one i need 40 I/O pins, and thinking of using an atmega2560 and just use a uart connection from my proc board to control the mega2560 to be just an I/O co processor. Also working on expantion daughter boards for my projects. So if i want to add a usb or RJ45 or something else, either with UART or 12c or something else. Putting mesanine ports so i just snap a module in. Make it so all my projects are build for application and just snap together. Not having to build a bunch of different PCBs for niche application. My house is completly automated with Home Assistant running in an esxi vCenter cluster on a rack and about 20 other servers and 15 or so other virtual machines. And then i have lights switches, systems, IoT, etc.. about 260+ devices being controlled wirh home assistant. My projects will allow me to automate more and get more data :)

[@PhilsLab]

That sounds great, Mike! I agree that the modular approach seems like the right way forward in that case. Would be keen to see some pictures once you're done! :)

[@ashishjog]

Can you make a tutorial on interfacing an external ADC like ADS8528 in daisy chained over SPI with STM32H7, or can you share some good resources. Thanks!

[@sanjikaneki6226]

on the DDR bank there are like 3-4 free pins why did you not use 2 of those and left the reference pins for proper references? Also how hot does that ZYNQ get? i heard that they can get very hot and most board have a decent heatsink over them +RAM ( or is that a plan of the future / when in prolonged use) Why you didnt add mounting holes on the edges/corners M2.5 or M3 would have been nice for putting the board in a box

[@rashid_urbanAgri]

WOW Really good tutorial. Can you please design related to WIFI router ,Mobile sim integration

[@bradleybaldwin100]

I've never heard potentiometer pronounced that way! Still learning the differences between US/British English I suppose.

[@boyfarrell]

I’ve not heard it this way before either and I’m British.

[@dukenuke2690]

Interfacing the Hyperram isnt quite simple since there is no free IP in vivado available for that. There are some some free IPs out there though. I managed to get a hyperRAM working with the openHBMC IP

[@humamshdidy5129]

Hi, I have ddr3 (3D3D16G72WB2723) and I would like to integrate with and test it with the Xilinx eval board, what board would you recommend, and do you think there is a better way to test it, thanks

[@Aleexc2000]

hi phil, I would like to offer you an idea for a possible video on the creation of a custom hardware based on the new arduino uno R4 Minima or WiFi. It is based on the Renesas R7FA4M1AB3CFM MCU, ARM Cortex-M4. It would be nice and useful to see how you can make it independently or embedded in your own project, explaining and showing how to load the bootloader, also mixing some sensors and external peripherals, accelerometer, microSD, etc... I hope you will listen to this idea. Bye bye.

[@justanotheranonymous4381]

Are these schematics available open source somewhere?

[@Rangeldangeldodo]

Hmm IPC4761 type 7 magic 🥰

[@sc0or]

I have to warn everybody that you can spend about 15 minutes on a registration on AMD web site, stucking with a password and solving their f.. bicycle/bike captcha. They are just crazy. I merely gave up was thinking to prefer another manufacturer, but on the last attempt their web site decided to register me.

[@tamaseduard5145]

👍🙏❤

[@AlexAlex10703]

yoo

[@PhilXavierSierraJones]

Immediately, I wonder why the serial number and the code is scrubbed.

[@hengzhou4566]

Can you interface FPGAs with HBM?