MOSFET Capacitance Explained

[@mdshifathossen5546]

Just clear my whole doubt Man. Many thanks., I have already searched about 2 hrs. to understand the concept.

[@jennyzhuang2351]

I watched your series while I was taking 170A and hoping would have you as my instructor for 174. But, it did not happen :( Now I'm in grad school, still watching your video to refresh my memory. Really good videos! easy to understand, no complicated concepts/words, and well organized!

[@NexusZen]

This is the best video about mos capacitance. Looking forward to seeing and learning more from you about analog device and design!

[@JordanEdmundsEECS]

Nexus Zen Thanks! You’re in luck, I am taking analog classes in my PhD starting next week :)

[@NexusZen]

Great ! Just so lucky to find such an awesome channel!

[@shazadkhan7946]

the best video for thetopic...no bushing around .... thank you

[@omniyambot9876]

thanks! I'm undergrad and Im studying it for hobby project and apparently these people are studying doctorates! I'm proud!

[@BrutalGames2013]

Thank you so much for this Video series!

[@JordanEdmundsEECS]

Of course :D it was fun making them

[@evaschmid2583]

Thank you so much! Greetings from Regensburg (Germany)

[@diptanilbiswas5657]

you are too good sir please keep uploading.

[@azknustian]

Dear Mr. Edmunds ! Its a wonderful video. You have explained quite complicated Mosfet Caps phenomenon in a very easy and comprehensive manner. However, i have a question. The gate to source and gate to drain capacitances are due to small overlap of mettalic gate plate and n+ source and drain wells. Why is it necessary to overlap gate, source and gate, drain regions ? Although the question may sound naive but i found it intriguing. If there is no overlap, these capacitances can be erdicated and make the design considerations relatively simpler. Looking forward to hear from you

[@JordanEdmundsEECS]

Not at all! That's an excellent question. Ideally you are absolutely right, there would be no overlap and we would just have a gate that *barely* ends as the source/drain begins. However, when trying to actually manufacture the thing, it turns out that level of precision is not possible to achieve, so process engineers intentionally build in a certain amount of overlap to make sure there won't be any space between the edge of the gate and the edge of the source/drain. If there was a space between the edge of the gate and the edge of the source/drain, you wouldn't have a continuous channel of electrons, which would mean no current can flow.

[@azknustian]

@@JordanEdmundsEECS Thank u so much for your response. I highly appreciated your responsiveness and command on the subject. Stay Blessed

[@alonsechan8178]

Thank you very much ! It was very helpful

[@mklarso9570]

Can’t thank you enough for your awesome lessons! :)

[@JordanEdmundsEECS]

Julio Elias Thanks :)

[@electronic_guy8471]

Hi Sir, If overlapping is so complex, why cant we manufacture without the overlap ? I heard that polySi came to play after this . If So, Can you explain the new process ? Please correct me if Im wrong

[@JordanEdmundsEECS]

Excellent question! It makes sense we would want to eliminate or minimize overlap to minimize stray capacitance. If we could manufacture a transistor with *exactly* zero overlap we would do it. The problem is that manufacturing these things is hard, and there is often a slight misalignment from one transistor to the next. If your overlap is zero, and your gate is off by even a tiny amount, your transistor won’t work because you won’t be able to form a continuous channel. I think the technology you are referring to is the “self-aligned gate”, which does minimize this overlap but still has a small amount due to diffusion of dopants.

[@AmanKumar-dc9by]

is that overlapping capacitance between gate n drain,gate n source same as Cgs and Cgd? or the overlapping capacitance is different from Cgs and Cgd?

[@jordanedmunds4460]

Great question. The overlap capacitance is only part of the story for Cgs and Cgd. There are other sources of capacitance as well (i.e. capacitance to the channel itself, which gets lumped usually mostly into Cgs and partly into Cgd, depending on its shape), but these are a good *absolute minimum* for the capacitance of Cgs and Cgd. You're not going to get lower than the overlap capacitance.

[@secsionx4240]

best prof

[@MPaulHolmesMPH]

So, a capacitor's switching losses would be the sum of 0.5 * C_i * V_i^2, for each capacitance/voltage every cycle?

[@JordanEdmundsEECS]

Yup! Assuming you define the capacitance in terms of the overall delta-V and delta-Q you would get the correct answer. This would represent the total energy put into the capacitor after a charging cycle. Once you discharge it you dissipate the remaining energy, so for a full cycle it’s 1 * C*V^2

[@rakshithakoriraj8469]

Worth watching.. really good

[@focu625]

This video is fantastic Sir....Can you do more content on CMOS VLSI Design...

[@magnuswootton6181]

but how fast does it go - the permittivity of free space has many 0's after decimel point.

[@truthfully470]

amazing! Thanks a lot for this very helpful video :)

[@TheMuhendistv]

I don't understand why static charges prevent it from acting as a capacitor. Can you explain that? Why do we need moving charges?

[@ameykulkarni7823]

Thanks for the video

[@JordanEdmundsEECS]

Thanks for ruling wisely over the savannah.

[@ameykulkarni7823]

@@JordanEdmundsEECS 😆😆😆

[@josephminginga8585]

Thank you, very helpful!

[@JordanEdmundsEECS]

Thanks!

[@unnimaya5681]

Thanks

[@navkaransingh3948]

in depth concept explanation sir can u suggest some refrence books for vlsi design ( beginneers ) thnx a lot

[@JordanEdmundsEECS]

Thanks! I found the book CMOS VLSI Design by Harris to actually be really good.

[@Abdoul_Rjoub]

Can you send me the link to download these videos?

[@JordanEdmundsEECS]

I think you can rip them off KZbin, right now they live on my non-networked computer xD

[@belongstozorax4640]

9:47 , and it becomes zaputlsya

[@anantadebnath7977]

How this capacitor works in single electron tunneling?

[@JordanEdmundsEECS]

Basically, when the oxide gets too thin, electrons are able to tunnel from the gate to the bulk. You can model the oxide as a rectangular potential barrier, you can use the band diagram to find out what the barrier height seen by electrons in the metal is and you presumably know the thickness of the oxide. This allows you to compute the tunneling probability.

[@shivammalviya3737]

He is in god's level

[@sharayuhajare7743]

Not satisfied

[@JordanEdmundsEECS]

Thanks! Care to elaborate?