Which to use , Asynchronous reset or synchronous reset ? Resets Explained || Reset synchronizer!!

[@komalpilani7029]

The best video to learn the concept in onw go!!!

[@KarthikVippala]

Thank you🙏

[@ashwinrs1514]

Great video, thanks a lot man

[@kunal1184]

Really great Explanation

[@KarthikVippala]

Namaskaram 🙏 , Kunal , thanks for the support, pls do suggest any topics for upcoming videos, , good luck and great health 👍😊

[@kunal1184]

@@KarthikVippala Some topics of Verilog like blocking and non blocking assignment,types of delay in Verilog ,as these topics are Been asked in many Interviews of VLSI

[@kunal1184]

@@KarthikVippala Namaskaram,Goodwishes and great health to u too..The videos u make have really good explanation 🤩🤩

[@KarthikVippala]

Sure👍

[@kunal1184]

Please make 1 more video on this topic if possible by giving examples, examples give really great understanding

[@porksandbean]

good refresher!

[@KarthikVippala]

Namaskaram _/\_ A M , Thanks for the support and love , good luck and great health :)

[@user-fw7sv7jc3q]

thank you the videos, do you conduct mock interviews ? please let me know..

[@KarthikVippala]

Namaskaram 🙏 sneha , no I don't conduct them , good luck, great health 👍😊

[@tophero165]

You are doing a fantastic job bro... Thanks for all your work. Can you also add a video explaining pulse stretcher modules?

[@KarthikVippala]

Thanks for the support good luck & great health 👍😊, please check my channel I have made a video on pulse to level converter . 😊

[@hongsenyu8108]

In industry, another drawback of the ASYNC reset is about DFT. With reset synchronizer, the final reset signal is internally generated, which means it cannot be fully controlled by reset input. You need two clock cycles to let the internal reset nets go back. EDA tools don't like this scheme when doing scan insertion for DFT.

[@kpark5467]

What about using a 2-input DFT-MUX at the output of reset synchronizer ?

[@優さん-n7m]

So how is this resolved, please tell us the whole story

[@antonymathew]

thanks Karthik.. a suggestion.. in light of this video , could you explain recovery and removal concepts for STA. i aways have doubt why setup/hold is not the terms associated with reset's timing analysis.

[@KarthikVippala]

Sure

[@tcliu8832]

Hi, thank you for your great videos, i have two questions about rest, please help me !! 1. As soon as Q1 goes to metastable, why does Q2 stay in "0" in the next clk edge? (why doesn't it pass the metastable occur at Q1 to Q2 , I saw you answer Lit scar that the input of Q2 is constant, but i don't get it..) 2. Why does synchronous reset doesn't cause metastable issue? Is it because of we can set a appropriate rst signal to the flip-flop?

[@KarthikVippala]

Namaste 🙏 prasanna kulkarni, thanks for answering , good luck & great health 👍😊

[@sprhbm8422]

@@KarthikVippala where is the answer

[@RahulKumar-oz2mc]

At 8:57 , master rst_n is getting high on another active edge of CLK, so isn't there possibility of timing voilation?

[@baswarajsghali2074]

Why does the second flop does not go into Metastable state?

[@theseeker1964]

is it possible for the either of the 2 FFs to go metastable when the rst_n goes low? (which I think is called is reset recovery time..thus could there be a violation of when the rat_n first goes low with respect to rising clk edge?)....that would not be good as the output of this circuit goes to "all" of the internal FFs. .or do we only have to worry about the removal of the reset (rst_n going high which I think its called reset removal time)? however this case (rst_n going high) will be protected by the 2-stage FF circuit which now produces a synchronous reset

[@ramyarajam6173]

Plz make a vedio for verilog course

[@KarthikVippala]

Sure on the way🤝

[@Arif-tz5tf]

Sir What if the the Q1 become low after the metastable state at the next pos edge of the clock then we get the master rst Q2 low as well

[@dhrv33]

I was asked a scenario, that in case of reset synchronizer circuitry, what happens if in case if logic 1 at the D of 1st rst sync flop is connected by async rst itself. Would it work?

[@litscar978]

does the 2nd flop also has asynchronous reset? If yes, wont it go to metastable state

[@KarthikVippala]

Namaskaram 🙏 lit scar , Yes 2nd flip flop is also async rst, but input is constant ,which will not violate , but at first flop input is changing . Good luck, great health👍😊

[@circuitsanalytica4348]

Interesting query....

[@sowmyahiremath8969]

Why are resets always active low? It has now become a convention to use reset as active low, but can you please elaborate why are resets considered as active low ??

[@sathwikkkunder7338]

why do most of the reset signals are active low rather than active high?

[@akashwayal8797]

when we apply the reset near to the clock edge what happens ?

[@ishansharma5289]

For ASYNC reset, when it is deasserted, it may go into metastable state. I understood this part. But why does is not happens when reset is asserted? What if reset is asserted at setup time of clock? I get it that reset does not depend on clock during assertion bcuz it is async reset, but since it is async reset why does it depend on clock during deassertion?

[@varunmajji6514]

thing us during deassertion ,you are making design active to recieve input,so if you recieve input withing setuo window there is possibility of setup violation

[@優さん-n7m]

reset will reset the register, how can it go into metastable state when it is being forced into reset?

[@ranjanparnami]

Thankyou

[@KarthikVippala]

Namaste 🙏 Ranjan Parnami, thanks for watching videos,good luck & great health 👍😊

[@circuitsanalytica4348]

Nice video, isn't it Ranjan....

[@simmimaster]

Sr flip flop is synchronous or asynchronous!?

[@KarthikVippala]

Namaskaram 🙏, SIMMI MASTER, it depends on the connections ,if all components connected with are synchronous then it is synchronous else it is asynchronous , thanks for asking, good luck & great health 👍😊

[@mounikabhuma8631]

Why active low reset always we use, is there any reason?

[@MrPumatube]

for power saving reasons, it is better to manipulate a zero voltage that mantain a high voltage up

[@arpitapatil19]

explain cdc and rdc

[@karthikperepa1981]

is there any difference if we use posedge reset instead of negedge reset in sensitivity list or any thing we can use?

[@circuitsanalytica4348]

Your functionality will change if you use negedge instead of posedge, so it is not advisable to use posedge instead of negedge or vice versa

[@indiandrums8591]

Why we use asynchronous signals...

[@unnatishah5457]

Content is good. But Please dont try to improvise accent.

[@KarthikVippala]

Namaste unnati 🙏 , thanks for the support, good luck & great health 👍😊