Learn Verilog By Examples - Dual Clock FIFO

This episode shows how a dual clock FIFO is constructed and how it can effectively synchronize pointers and reset to achieve clock crossings of wide databus.
Code :
bitbucket.org/...

[@pavankumar-tt1wx]

Sir,, do more videos on verilog by examoles please.. Your videos are great knowledgeable

[@matthewstridiron]

This is a really helpful video about how to build a dual FIFO! Would you happen to know how to implement a shift register for this design? I think making one for a single clock is relatively straightforward. My concern is that the shift register will have trouble given that there are two clocks.

[@TheMindGrid]

Are you saying instead of memory elements, you want to implement Flip-Flops with shift registers ? My question is why do you need that ?

[@matthewstridiron]

@@TheMindGrid I am building an FIR filter for a MAC operation. The way it works is that I'm going to be taking data from memory and appending it to the queue. Since data is constantly being added to the queue, I needed a way to pop off the frontmost element from the queue once it becomes full so I can feed it into a distributed arithmetic module. Perhaps I gave you the wrong question, as the distributed arithmetic module happens to require a shift register that is independent of your design. What I do need to know, though, is how to pop elements off the queue. Is there a way to do that?

[@TheMindGrid]

@@matthewstridiron The FIFO can also act as a queue. On the read side, you can use the depth of queue, and if depth of queue is greater than some value, you can start to read the data from the dual clock fifo and then feed that data into your compute engine.

[@rashmits1834]

Hello sir. Thank you for the video. Sir what is areset_n_ms? why is it required?

[@TheMindGrid]

Hello @Rashmi - The asynchronous reset going into this module, has to correctly reset both write and read domains. For this purpose you have to synchronize the reset first to the write clock domain and read clock domain accordingly. Timing a reset is important in some blocks that maintain pointers or other logic that has to come out of reset in a known way, otherwise it can come out of reset and star counting incorrectly. This is why we use timed resets and synthesis tool has to close timing on condition when we come out of reset. The _ms flop is the first flop when you time the reset. You have to normally flop two times before using an asynch signal. This helps reduce metastability probability. The second flop after _ms is _wr which is used as reset in write domain. Hope this makes sense.

[@radhikaswarnkar7849]

When shall we reload wr_ptr and rd_ptr?

[@TheMindGrid]

Not sure what you mean ? The write and read pointer should keep changing based on read/write requests ?