Lec-33 static timing analysis.wmv

[@TCN8202]

0:03 Intro 0:32 Start and Outline 0:53 ASIC Design Flow (Front-End) 5:52 Back-End Flow 22:26 Timing Analysis 28:32 Types of Path Inside a Chip 29:09 Typical Path 30:26 Typical Data Flow 31:59 Setup & Hold Window of Flip-Flop 36:25 Setup Equation 46:55 Hold Equation 51:09 Choice of Clock Frequency 53:29 Role of the STA Engine 58:13 Analysis Corners 1:04:30 Design Constraints (part I)

[@dhaneshprabhu72]

Thanks for this bro

[@manaslahon]

This is the probably the most fluent, crisp, to the point Lecture on ASIC flow and STA I have gone through. The way Prof Tuhin builds the background and explains things makes this clear even for the beginner.

[@Hav0c1000]

I love the sprite commercial at the end of the video!! Great lecture overall. Basic concepts explained very well!

[@sang625]

😂😁

[@rawl9411]

Good one.. One point to add: We use D-ff in designs instead of JK to allow only two states, set or reset, in the ckt. Toggling and no change states are not of use generally...

[@sanjeevyadav-lw4ky]

@42:14 why we have not captured the first launched data at first captured edge?

[@dhaneshprabhu72]

It cause race around, then all the transitions in all FFs happen at juts 1 clock edge itself which doesn't give sequential behaviour

[@DestrovPro]

Thank you sir! It was a brilliant explanation. Enjoyed re-learning these important concepts. Loved that every concept was explained in a detailed manner! Hats off to you Sir!

[@vinayteja4402]

Can you explain STA with full example , like with small circuit , not with single gate . Am not getting how it will caliculate setup and hold for a circuit . Will it feed random pattern ? Thank you for nice explanation

[@76ainani]

Excellent, practical and well organized lecture! Thanks a lot, Prof!

[@dhaneshprabhu72]

I have a question. How to do we design the basic gates/flip flops tip have setup and hold time as per our requirement? Can someone help me with this

[@madhavrabinbipin2116]

i had particular doubt about hold time equation before i saw this lecture. myself from iit bombay

[@arjun9273]

2020 batch?

[@madhavrabinbipin2116]

@@arjun9273 2019

[@phoenixbird7030]

More explaination with clear steps on how static timing analysis and dynamic timing analysis using practical examples would have been more helpful,demonstrating with numerical examples with different practical circuits for the statements for set up, hold time equations, possibility of scaling down the frequencies for chip,would have been more helpful than mearly explanining the equations and giving the statements....even though some knowledge is gained on static timing analysis...still there are many doubts left in my mind by the statements given without clear explaination of how it is aschieved ....

[@sang625]

True

[@charleslin6928]

I am a ic backend engineer. I show my working experience on the following blogs www.52-ic.com

[@dhaneshprabhu72]

Thanku sir for such a wonderful explanation with practical examples

[@vinayteja4402]

Why R-R path from clock to input of the register ?

[@TCN8202]

Thank you. Thanks to IIT Kharagpur and Mr. Tuhin Subhra Chakraborty for this excellent course.

[@hrishikeshadn1]

Beautiful concept, beautifully explained.thank You Sir

[@kushalshah5512]

Lecture overall is good. Many basic concepts are explained.

[@ShreyasBharadwaj]

6 Lakh salary :D...Superb lecture by the professor :)

[@vinaykushwaha5223]

Now in Qualcomm

[@chaturbhujrajendran4995]

How I wish I was in an IIT.

[@ChillWithAbhishek]

Where will I find all the videos in this course . I searched on NPTEL but they are not there . If you are having the remaining videos please upload them !

[@subhamgoyal5289]

www.satishkashyap.com/2012/02/first-course-on-vlsi-design-and-cad.html

[@Gggggg172eyeyeurhuwue]

But I still dont get it , what is the specific signifiance of the word STATIC ?

[@zackmax]

You don't require switching activity in order to analyze the clock and data propagation. In short the analysis is done solely based on the netlist itself without simulation.

[@adityamitra]

is synopsis tool available as student version?

[@RandomMusingsOfLowMelanin]

Shouldn't it be Min time instead of max time while defining hold or setup time?

[@chetana17]

yes it should be Minimum

[@RandomMusingsOfLowMelanin]

+Chetan A Thanks!

[@sumaiyashahoo]

I have doubt regardding his setup time equation.: Shouldnt it be T - Tskew? @ 45:09

[@LinhHoang-zi9mt]

Are there other lectures from this Professor? He's pretty good.

[@subhamgoyal5289]

www.satishkashyap.com/2012/02/first-course-on-vlsi-design-and-cad.html

[@sivasree9]

Hi all.. Where can i get all his lectures so that i can download and go through.. Help me out guys..

[@durgaprasadkornipati4608]

If you subscribe then automatically you will get all lecture videos of him. If you want to download the video just do one thing type SS after www. in the searchbar. You can then have the chance to download. But remember after opening the respective video only you have to do the above process which i have mentioned. Hoping so it can be helpful for you..!! Thank You

[@MatrixOfDynamism]

formula based?

[@av_410]

Thank you....this was perfect!

[@GundalaBabu]

why it will go up ? I am not sure :-) thanks a lot sir..

[@warraich114]

Thank you !!! Very good lecture indeed !

[@sayanibhowmik8344]

All those habi jabi stuff😂

[@ingnilesh]

Thanks SIR

[@Ravi-ot6xj]

the weird background sound is so distracting wtf

[@lolhahahaha1370]

bihari lec. h koi h

[@robby1992]

GG

[@PamandeepSinghPuri]

Bekaar teacher hai