Lecture 9 (CHE 323) CMOS Process Flow

[@amentothatt]

Thank you so much. Prof. Mack! You just gave me a very clear whole picture about CMOS process. I just subbed you without hesitation.

[@ruizeng2374]

Thank you professor! This is useful!

[@SouravChandaElectronics23]

Thank you Sir for such a clear cut concept about the process flow.

[@rajrajput2023]

Have prepared notes from these vedio??

[@srikarthikkadapa4108]

Hello chris how to decide the depth of n well and what must be the energy required by the diffusion atoms to diffuse to certain depth. Is the diffusion happens in perfect rectangular in shape.

[@Jarrod_C]

why are you connecting metal to polysilicon? and why is it far away from the cmos region? It doesnt look set up to attract carriers into a channel.

[@thcoura]

I never get why we need highly doped p and n close to one of transistor connections. Can the professor explain why?

[@kitten_with_bad_breath]

It's to make ohmic contact.

[@ChrisMack]

A PDFcopy of all the slides in this course are available at: www.lithoguru.com/scientist/CHE323/course.html

[@Jarrod_C]

why not put photoresist over the polysilicon gate to protect it, it feels like your contaminating it. why do you have a thin layer of oxide while you are implanting dopants don't you want it to clear silicon?

[@thcoura]

Roughly how thicker is the gate bar to not let the implantation damage the gate isolation in the self alignment process?

[@ChrisMack]

The answer depends on many things. A range of gate thicknesses are possible depending on implant energy.

[@manojsingh-bs2px]

Sir link of PowerPoint or pdf of lacture materials.

[@applemlgb]

8:31 p+ VDD tap?

[@SIC66SIC66]

Great explanation! Why do the metal layers get so much larger the higher they are in the stack? Or are these maybe mainly the power lines?

[@ChrisMack]

The lower metal lines are used for local interconnections. They tend to be short, so it is OK if they have higher resistance. The higher metal lines (towards the top of the stack) are for longer distance connections, and so we want thicker and wider lines for those long connections to keep the delay times short. Power and Ground lines tend to be the fatest.

[@SIC66SIC66]

Chris Mack Ah, thank you very much! That makes sense. The connections to the outside world are at the top, so does that mean there are very small wires going from the bottom to the top to carry the data? Or is all wiring on a certain layer the same size?

[@ChrisMack]

Check out lectures 28 and 29 on interconnects: kzbin.info/www/bejne/fanTYpaImsR_r80

[@SIC66SIC66]

Chris Mack Thank you, I will. You have made a great channel Chris! This will waste hours and hours of my life the coming weeks! I recently bought a microscope and some acid to decap some chips. Nowhere near Zeptobars level, but I love this stuff :D I appreciate the time you spend on this :)

[@therandomchannel9226]

You forgot to mention LDD and reasons.

[@ChrisMack]

LDD - lightly doped drain, is a way to tailor the dopant profile near the edge of the gate to reduce the electric field and the number of "hot" (energetic) electrons that have enough energy to penetrate the gate oxide.

[@therandomchannel9226]

i.e. known as Hot Career Injection :) Your explanations are good. Can you make a video on the difference between CVD (its types, methods), ALD, Sputtering, PVD combined with Epitaxy lecture. It is a little confusing. Also your explanation on 13.56 Mhz standard frequency saved me. Thanks for that.

[@therandomchannel9226]

Also, a video on SPC ( I have seen it but it's too short), 8D, 5Whys, 6Sigma, etc - in the domain of Semiconductor in detail would be awesome. Also how tech nodes differ in Analog and Digital would be great too :-D