Modules & hierarchy | Lets Learn Verilog with real-time Practice with Me | Day 7

[@darya2615]

УЧИМ ВЕРИЛОГ ВСЕЙ 108 СПАСИБО ОТ БУРЯМОКВА

[@mayankkundriwal9261]

Thank you for this i am learning verilog in my college too and this series is a motivation for me 🙏

[@asifsir2689]

module top_module ( input a, b, c, d, e, output [24:0] out ); wire [24:0] top, bottom; assign top = { {5{a}}, {5{b}}, {5{c}}, {5{d}}, {5{e}} }; assign bottom = {5{a,b,c,d,e}}; assign out = ~top ^ bottom; // Bitwise XNOR // This could be done on one line: // assign out = ~{ {5{a}}, {5{b}}, {5{c}}, {5{d}}, {5{e}} } ^ {5{a,b,c,d,e}}; endmodule

[@dhanalakshmi5930]

Thank you 🙏

[@Dsay_Diablo_27s]

Me here complting 30 days work in single day… well thankyou bhaiya for videos

[@anandbvs143]

Nice ❤

[@shailendrakumarmishra2407]

thanku 🙂

[@mounikadas2090]

i get errors please show solution for last vector question

[@supriyaarashinagodi8915]

Hi I didnt get the pervious solution of vector.Can you please send the solution

[@whyRD]

Oky sure will briefly discuss on it in episode 9

[@rk0812]

❤❤❤