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Setup and Hold time inside Latch

  Рет қаралды 11,095

Team VLSI

Team VLSI

Күн бұрын

Пікірлер: 22
@vikaspatel656
@vikaspatel656 3 жыл бұрын
this helps me a lot sir. thank you so much sir and keep uploading more videos related to STA.
@TeamVLSI
@TeamVLSI 3 жыл бұрын
Sure Vikash.
@ytaccount9420
@ytaccount9420 3 жыл бұрын
Whatsapp group is full, please create a new group. Very helpful videos. Thanks alot.
@TeamVLSI
@TeamVLSI 3 жыл бұрын
please find the latest group link in www.teamvlsi.com/p/contact_8.html
@krishnachaitanya8609
@krishnachaitanya8609 3 жыл бұрын
Hi Team! This is some fabulous work you're doing by giving clear cut explanation of the most imp topics in vlsi. The whatsapp group is reported as full. is there any additional group to join?
@TeamVLSI
@TeamVLSI 3 жыл бұрын
Hi Krishna, Thanks for your appreciation. Just we have created a new whatsapp group Team VLSI (Group -3/3). You can join there and wait for few days to come more people to start discussion. Group link: chat.whatsapp.com/GJKvTsZ1WQz81K19iqrTIX
@amalenduaman7239
@amalenduaman7239 Жыл бұрын
@@TeamVLSI sir,whatsapp link is not working
@nikhil00017
@nikhil00017 3 жыл бұрын
Nice video. Can u please make video on layout dependent effects??
@TeamVLSI
@TeamVLSI 3 жыл бұрын
Hi Naveen, Can you explain a bit more exactly what effects you are talking about.
@AmmammaNanammakathalu
@AmmammaNanammakathalu 3 жыл бұрын
If timing violations are at block level what fixes you make. If data path timing is optimized.
@TeamVLSI
@TeamVLSI 3 жыл бұрын
If there is no scope in data path, then we should look for clock skewing option.
@TeamVLSI
@TeamVLSI 3 жыл бұрын
If there is no scope in data path, then we should look for clock skewing option.
@AmmammaNanammakathalu
@AmmammaNanammakathalu 3 жыл бұрын
Thank you guys
@asherpaul4450
@asherpaul4450 3 жыл бұрын
Can you help us to have Verilog code for calculating fft and ifft
@TeamVLSI
@TeamVLSI 3 жыл бұрын
Not much idea on this, Expecting help from community if someone has idea on this.
@asherpaul4450
@asherpaul4450 3 жыл бұрын
@@TeamVLSI if it is given it will be a great help for our final year project. Our project is n point fft and ifft in Verilog and implementation on FPGA
@anumaha3824
@anumaha3824 3 жыл бұрын
Sir I want join your wattsapp group ...it shows group is full...please make another group sir
@TeamVLSI
@TeamVLSI 3 жыл бұрын
Here is the latest group link. chat.whatsapp.com/HVyyJRmKDXQJFvBs7ko5qf
@saurabhsharma-ry9cw
@saurabhsharma-ry9cw Жыл бұрын
Noicee
@TeamVLSI
@TeamVLSI Жыл бұрын
Thanks @saurabh
@himanshupatra1991
@himanshupatra1991 2 жыл бұрын
Seems like the whatsapp group is full.
@TeamVLSI
@TeamVLSI 2 жыл бұрын
Hi Himanshu, Please try the updated links on this page. www.teamvlsi.com/p/contact_8.html
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