Clock Uncertainty in VLSI | Why clock uncertainty | Factors in Clock Uncertainty

[@kankanalasamhithachowdary236]

We add skew in setup uncertainty only right( given formula), then why we added seperately at 13:15

[@TeamVLSI]

Hi Kankanala, We consider the skew in uncertainty only in preCTS stage. Once the clock tree is build, we have actually skew so we dont consider the skew in uncertainty. Watch again at @11:27, it will be clear.

[@dn2358]

Keep uploading sir👍🙏

[@TeamVLSI]

Sure 👍, keep supporting...

[@SUDIPTODUTTAGUPTA]

Thank you, sir. I have the following query: If the jitter source is from the common CLK, why do we need to consider it in Setup uncertainly? Shouldn't the jittered clocks (FF1/CK, FF2/CK) edges be moving in the same direction?

[@TeamVLSI]

Hi Sudipto, Yes, right. But in setup analysis launch and capture clock edges are different, and jitter is associate with edge.

[@SUDIPTODUTTAGUPTA]

@@TeamVLSI Yes sir, I missed that part. Thanks for the explanation.

[@niteeshfunworld4656]

Nice video and explanation

[@TeamVLSI]

Thanks a lot Niteesh. Stay tune and keep learning.

[@yuxiang026]

Thanks, a really good video. And it will be better If here are subtitles

[@TeamVLSI]

Thanks Yuxiang, It is my pleasure that you loved the video. I will try to add subtitle.

[@komarashiva2091]

Sir in pre-cts u mentioned latency is negligible then how u calculate the skew(capture latency - launch latency)

[@vamsikrishnagedela8990]

hi sir, at time stamp 13.58 we are using uncernity (skew +margin+jitter) then why another skew componet ...is this calculation in post cts

[@joshnareddy7480]

Uncertainty will relax after CTS has built and we will keep uncertainty for synthesis to meet setup timing

[@KomalsCreations_]

Thanks for explanation

[@TeamVLSI]

Always welcome Komal, Keep watching, Keep supporting...

[@nghiahiepbuiphuoc8946]

It is a great video!!! I think the accuracy check (such as Min pulse width check, Min period check, clock as data check, ... ) is an interesting topic. Could you consider my suggestion?

[@TeamVLSI]

Thanks for the tips!

[@nanoelectronicsdemystified]

why are we considering setup/hold margin in uncertainty while we are also considering it for setup/hold calculation? (The margin in uncertainly refers to something else I think)

[@TeamVLSI]

I would love to see other name, If you have details Please share.

[@joshnareddy7480]

Can you please do video on clock gating and asynchronous checks in vlsi

[@anithasabhavat6064]

Hello sir, Who will set this uncertainty value? Synthesis ppl?

[@TeamVLSI]

Yes

[@akashwayal8797]

sir what is setup and hold margins? why are they required?

[@TeamVLSI]

Hi Akash, Positive slack is called the margin. In a particular data path if you want to fix setup, means you are going to reduce the delay of that data path, It may violate your hold. so you must have hold margin on that path and vice-versa.

[@akashwayal8797]

@@TeamVLSI Yes thank you !

[@janapadakannadasongs]

how to define the uncertainty value in sdc?

[@TeamVLSI]

Hi VP, Watch the full video, although at time 12:30 , it is explained.

[@merrygo7189]

Why uncertainty is High in Half cycle paths?

[@arunpandiyananbarasu1455]

Nice sir

[@TeamVLSI]

Thanks Arun. keep supporting...

[@vikaspatel656]

in RAT calculation you have taken time period in setup analysis but you have not taken time period in the hold analysis . why ???

[@TeamVLSI]

Hi Vikas, The answer is simple, We check hold on the same edge not on the next edge like setup.

[@shrikanthramanagara2382]

THNK U

[@TeamVLSI]

Welcome 😊