How to Design Synchronous Counters | 2-Bit Synchronous Up Counter

[@MC54483]

I've watched all of these lecutres in order an man I am feeling amazing for my exam thank you so much sir you are a life saver!

[@DrAwesomeOmfg]

really great! thank you. It's actually very difficult to find simple examples of counters. Most are 4-bit asynchronous

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True 😂 at 2 am tomorrow 8:30 we have exams

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Best tutorials on youtube on this subject. Thank you!

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Crystal clear description

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watching these videos at 1.5x speed lol...exam tomorrow ..yup m screwed . ..u are a saviour ..thanks a ton!!

[@nirmalmondal1494]

sir you said is there any restriction on whether Q1 is MSB or Q2 is LSB, bcz in earlier video you treat last FF output as MSB

[@Letgocomp.444]

First one should be lsb. So q2 in first ff

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Love you Neso Academy!

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Nice explanation Sir... 👍

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[@bios546]

Sir, you demystify DE really well!

[@nandhinin2475]

Can you please clarify is this up or down counter because the MSB and LSB interchanged so output equation also changed

[@mohamedfathy-ml6dm]

amazing explanation,sir

[@rishabchakravarthy79]

Sir, why u r considering Q1, Q2 for finding j1, k1,j2,k2 using k-map instead of Q1*,Q2*

[@aswinp888]

We only care about the present state during the K map

[@3sh66]

sir can you make detailed videos on identification of symmetry in given function which are very important

[@arnie8958]

trust me i am doing eet from a canadian institute but I watch his videos for clarification as my dp2 prof sucks!!

[@user-lw5vg1zd6l]

thank you , you saved my life

[@NicoRealm7]

When we make the K-map cells for determining J1, K1, J2 & K2, why do we consider the present state values of Q1 & Q2 instead of next state values of Q1 & Q2 ?

[@satadhi]

hi can u explain the logic behind making the circuit excitation table, i mean why we are doing this thing ? thanks

[@jeremyheng8573]

good explanation!

[@tanay841]

Nice explanation ! But sir I think in the circuit excitation table, Q1 and Q2 should be interchanged.

[@LonerFactsClub]

I too have the same doubt.

[@ashutoshmishra372]

wonderful explanation sir!!. but can we design a counter using a d flip flop?

[@umutdevrimkaya4258]

of course

[@toushi100]

you make everything easy

[@hasiyaamadu1268]

when you simplified using the k' map,q1 and q2 taken as the input.but should it be q1 and q+1?

[@Confusedalien1133]

For people getting confused about MSB LSB!. It is a "synchronous counter" i.e one flip flop doesn't depend on the output of the previous flip (getting clock from the previous one) like in async counter!. So initially he took q1q2 (with q1 as MSB) and he did the procedure with the same! and in the diagram eventhough he drew q1 first and q2 second EVEN if he drew q2 first and then q1 IT DOESN'T MATTER!! what matters is what YOU CONSIDER AS MSB. So if q1 is initially considered as MSB then in the FINAL the same q1 MUST be taken as MSB and fed to some other circuit (perhaps?) but the representation doesn't matter!. ALTHOUGH things would've been clear if he had taken q1 as q2 and q2 as q1!. Ask me any doubts if u have!

[@himanshushekhar9501]

Alright, bro how is J2 & K2 coming out to be 1 ? Using k-map

[@-A-Rohith]

you explanation is too good thank you this may clarify the doubts of all.

[@Confusedalien1133]

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[@maheshwar_mr]

the final diagram is wrong.You have considered Q1 as the MSB throughout the entire video. But in the end, you drew the diagram Q1 as LSB. The flip flops should be reversed.

[@shubhnamdev5265]

no the circuit is corect. bcoz he fed i/p frm ryt to left.. so its the same case when we fed i/p lft to ryt and see o/p in inverse form(i.e. last f.f have msb) so either u inverse o/p or i/p.

[@kuldeepchinwan2852]

Yes final diagram is wrong ..q1 and q2 are interchanged

[@RahulMadhavan]

I think as the circuit is synchronous (without feed forward), the placement of the flip flops shouldn't matter as long as we know that Q1 is MSB and Q2 is LSB

[@karthi6843]

yes crt

[@karthi6843]

yes ur crt the logic diagram is wrong i found in book

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Very goood video! U make my life. have a question: why the analog circuit is not updated? :(

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[@md.abdulmuhaimeenkhan2803]

Will the circuit be same for positive triggered?

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Agar video galat hogi to koi problem nahi sir aap nayi bana do hume koi dikkat nahi hai hume sirf aapse sikhne me achaa lagta hai

[@bhakti13]

for J1 k-map, dont we have to use Q1 and Q1* ? since our o/p is dependent on those two? and llly for the rest kmaps?

[@angrynoobgaming3287]

i have the same doubt if you answer to this query , i would to very happy to know the answer

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please make vedioes on computer organization and architecture

[@abdulrashidabubakar3673]

Thank you sir

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[@rishabchakravarthy79]

I typed it wrong sir the previous one i.e instead of using Q1 and Q1* for finding j1 using k-map u have used Q1 and Q2.why sir ? Would you please help me in this aspect

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I like how he wrote flib flob. It's something i also can't resist to write, sounds so much funnier

[@gsaivamshi5856]

Sir I have 2 doubts related to this topic 1. Why have you taken clock as neg egde?? 2. Since Q2(J2,K2) are taken as LSB's .. should it come first in the logic circuit diagram??

[@faneeshbansal]

Yes it should be come first 🙂

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I have an exam and rn binge watching hell ya...

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I finally understood this!!!!!!

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[@Surendiran-o8g]

In this video, u made Qa as msb and Qb as lsb this will change the nature of counters .....where as in all other videos the output will be displayed in the form of lsb to msb but in this video it's vice-versa?

[@GauravGupta-se6xw]

subscribed for this one.

[@parthshinh1858]

Can we use D FF to make counters ? No right becoz toggling won't be possible then right but you said we can use JK or T or D any in this video please explain ??

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2 hours before test. I've miss sooooo many lectures and I am studying whole night on youtube and I am dying : (

[@ElifArslan-l9g]

thank you

[@liveitwithnidhi772]

great stuff👌

[@reema6540]

i have a question .. in clock it is negative edge since it is up counter ? what is the reason that you choose clock negative ?

[@prashantajabe2693]

you explained wrong Q2 must be in place of Q1. you should correct it

[@zxynb]

if designing a 2 bit down counter, the clock should be positive, right?

[@-Engineering01-]

I think the final diagram is wrong,you had to switch Q2 with Q1.but even so I thank u for this great tutorial.

[@yawarhayat5628]

Nope it was right

[@-Engineering01-]

@@yawarhayat5628 No,At start Q2 was LSB and Q1 was MSB.He did mistake at 12:22 while designing diagram. İf u designing a up-Counter then you need to start with LSB byte and then u keep going adding bits from LSB to MSB byte one by one(Q2+Q1) ,otherwise you would make down counter.

[@yawarhayat5628]

@UC4WsFDbcR48Q6BUyPElZ0XQ It won't matter in synchronous counters because outputs aren't fed to clock unlike asynchronous counter...

[@-Engineering01-]

@@yawarhayat5628 7:07 He decided Q1 is MSB and Q2 is LSB ok ? But Q1 output at Final diagram had to be interchanged with Q2.Where am I wrong at? Please look at video again.

[@debrajroy1290]

I am confused about mSB and LSb ..pls assist me...is the diagramatic representatio correct?? IS not that Q1 should be at right as its MSB

[@MRCOOL-vz8fn]

Thanks a lot sir :)

[@MrLpgd]

In your circuit diagram, You've shown Q1 as LSB, but in the excitation table you're using it as MSB. Please correct it.

[@nandhinin2475]

S wrongly derived

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I bet u miss koscisenely in Arsenal

[@aliabdulmalekalhaj1867]

greetings from depths my heart

[@Homayon-Malik]

Sir I don't know why but I think there's a mistake in step of k-mapping, you didn't differentiate Q1, Q2, Q1*, Q2*

[@btsindianarmygirl995]

Thank u sir