Digital Design & Computer Arch. - Lecture 16: Out-of-Order Execution (ETH Zürich, Spring 2021)

[@alpozen5347]

checking in from EPFL :)

[@dylanvernon1022]

During the professor's discussion of the unknown address problem, I was thinking about some potential optimizations. Would having a dedicated unit for computing addresses improve the processors ability to dynamically schedule load and store instructions? This addressing computation unit would be able to quickly compute the address using basic arithmetic operations and provide it to the scheduler for data dependence checking.

[@向宇-d4b]

address calculation may also depend on former ld/str instructions

[@jamespike-un1uv]

the critical path is that cpu need many cycles to fetch or store data from memory(or cache), and we don't know whether the instruction we are going to dispatch overlap with the older s/l instructions.

[@baobaolong423]

MIPS = Microprocessor without Interlocking Pipeline Stages

[@snehamoypatra9786]

Is it useful for digital design for power electronics converter

[@jatinder640]

Digital ckt. Design : are you kidding me? 😂😂😂😜😜😜

[@sushilece]

Slide 20, Cycle 9: There is 1 adder in the machine, how are E4 and E3 are getting evaluated simultaneously. Am I missing something?

[@nevilpooniwala3874]

I think the answer to your question is that the adder used is pipelined. Similar to how we had a pipeline in-order processor, we have a pipelined adder which can have instructions executing in different stages.