Onur Mutlu - Digital Design & Comp. Arch. - Lecture 17: Superscalar & Branch Prediction I (Spring21)

[@chaozheng2922]

These lectures are amazing, sincerely hope that you will publish a textbook based on these lectures.

[@dylanvernon1022]

A major roadblock to increasing performance centers on combining the benefits of data-flow and sequential architectures. The instruction scheduling unit must have sufficient information to organize instructions effectively, however, the scheduler only as access to a limited window of execution. If the scheduler had access to the full program context when it scheduled an instruction, it could optimally schedule that instruction. What is the most efficient way to expose the scheduling unit to the full program context without hiding the program's sequential order? It seems like the CPU requires access to at least two data structures: 1) the complete data-flow graph and 2) the compiler produced binary. If there existed a mapping between nodes of the data-flow graph an instructions within the compiler produced binary then the scheduler could refer to the appropriate data-flow node before scheduling each instruction.

[@JonMasters]

15 bytes 😀