PCB Design for EMI & SI - Phil's Lab #64

Tips and best practices for designing PCBs with respect to electromagnetic inteference (EMI) and signal integrity (SI). Covering fields & energy, frequency in the digital domain, rise & fall times from IBIS models, critical lengths, stack-up, traces and termination, vias, reference planes, and separation.
Mixed-signal hardware design course: phils-lab-shop.fedevel.education
[SUPPORT]
Free trial of Altium Designer: www.altium.com/yt/philslab
PCBA from $0 (Free Setup, Free Stencil): jlcpcb.com/RHS
Patreon: / phils94
[LINKS]
GitHub: github.com/pms67
Rick Hartley video: • [LIVE] How to Achieve ...
[TIMESTAMPS]
00:00 Introduction
00:34 Altium Designer Free Trial
00:55 JLCPCB & Git Repo
01:15 Signals, Energy, and Fields
02:02 Microstrip and Stripline
02:49 Frequency in the Digital Domain
03:34 Highest Frequency of Concern
04:08 Rise/Fall Times from IBIS Models
08:19 How do we Control EMI/SI?
09:20 Stackup
12:00 Traces and Termination
13:21 Critical Length
14:47 Vias
16:08 Reference Planes
17:33 Separation
ID: QIBvbJtYjWuHiTG0uCoK

[@Miguelocod]

It would be very interesting to see some measurements on the good vs bad tracks/routing

[@JediOfTheRepublic]

If only Altium had an actual hobbyist license. It's clearly only geared towards the industry.

[@SpinStar1956]

Thank You! Fairly straight-forward when you think it through. Always amazes me that PC-motherboard manufacturers can make such reliable high-speed circuitry. Really appreciate your making this video...

[@7alfatech860]

Thanks for pointing out the paths taken by electric and magnetic energy/fields. Really helps with visualising good placement of traces.

[@AngryMosfet]

Oh man, I can't wait for the video with Dr. Min Zhang, that's going to be very informative. Thank you Phil for all your effort and hard work you put into these videos.

[@harishrao2952]

Best Explanation at one place, thanks for the video

[@metebalci]

Yesterday I was downloading some CAD models from ST’s website and wondered what is this IBIS thing. Many thanks for all the great content.

[@tcurdt]

There are some great videos about this online. But yours is really to the point and much more tangible. Great stuff.

[@PhilsLab]

Thank you, Torsten.

[@AlkNA]

Great and informative video as always! You keep me motivated to design my own boards and apply knowledge shared by you and thank you so much for that! Keep the good work up!

[@PhilsLab]

Thank you - very glad to hear that!

[@johnstephenson4428]

Another great lecture loved the layout of the lecture easy to take notes just like college! Thanks Phil keep them coming!

[@PhilsLab]

Thank you very much, John!

[@sergioriveros5873]

Fantastic Summary... thank you very much for sharing

[@remy-]

This is a very good summary for amateur /beginning pcb designers! Well done.

[@PhilsLab]

Thank you, Remy!

[@wyattr7982]

This is perfect I was just trying to explain this concept to a fresh out of school coworker. Ive sent him enough videos from you and Robert Feranec already he refers to you guys as “your buddies Phil and Rob”

[@wyattr7982]

Have you ever worked with MIPI cameras or displays? Weve having a hell of a time getting it our camera interface to work correctly and im thinking its an signal integrity problem

[@DaSmik101]

@@wyattr7982 i'm working as an SI/PI engineer full-time. I can help you out if you contact me. Drop me a PM and we'll get in touch.

[@robiniddon7582]

@@wyattr7982 ours mipi CSI interfaces have always just worked ... but you do need to hit the specified differential impedance with reasonable tolerance. More likely than SI fail is sensor/soc mismatch on expected signalling. If you have a working reference design for your soc I would be inclined to try the reference sensor on your board (you may need a patch board). You know thst the drivers are ok for the reference sensor. If it doesn't work with the reference then it might be SI. In my experience mipi emc issues are more common than SI leading to non functional interface. YMMV obviously!

[@manobendro]

Learn lots of things. Great work. Keep it.

[@farshaddehghansanij7398]

Thank you so much! I gained valuable insights from this video and eagerly anticipate the next one to explore the EM test board. Have you shared it yet?

[@makarandgadgil1579]

Very good explanation & concise too!

[@kmacademy6742]

Amazing video, just wanted to highlight that thin prepreg layers are a tradeoff between manufacturability and performance. Sure, you get a better containtment of fields with thinner prepregs but in turn you need thinner traces to hit a target impedance especially so for differential pairs.

[@BM-jy6cb]

I went off and watched Altium's video and you're right - it's essential viewing for anyone who wants to lay out boards properly, but Rick presents it in such an interesting intuitive way that it's worth watching even if you are just curious about the topic. It's long, but the time flew by for me.

[@PhilsLab]

Completely agree. I've actually watched it more than once - information in it is a game-changer.

[@idk2412]

@@PhilsLab I absolutely agree, BUT, it seems that within the power electronics realm not many adhere to his thought process. I've seen very established companies that are passing safety regulations, not using this methodology. For instance, 4 layer boards that are carrying 80 A plus continuously, where in a section of the board all 4 layers are being used as the positive side or negative nets. So, no interleaving Pos + GND + POS + GND, just POS + POS + POS + POS. Or, vise vera with negative. I find trying to bring the philosophy over to power electronics more challenging, especially when creepage requirements come into effect. If you could dive into a power electronics example, like, a high power rectifier for data centers or DC DC supply, that would be amazing. You would be able to tie many subjects into the video, so, it wouldn't be super niche. Anyways, cheers, like your vids!

[@rallymax2]

The test board is a great idea!

[@bartek153]

Brilliant video Phil! Really good.

[@PhilsLab]

Thank you, Bart!

[@_a_x_s_]

First got to know the IBIS model. That’s really helpful as I sometimes got lost in the “max” rising time and the other parameters.

[@PhilsLab]

Thanks, exactly - really helpful to know!

[@helgeb5403]

You never fail to amaze me. I expected to learn something but i learnt so much more than expected. Great work. Please keep it up. Can you give a short explaination how and why termination of lines work?

[@KopikoMayorda]

Long story short. If you terminate a line to the same as the wave-impedanze of the wire you dont have any reflection. r =Zt-Zw/Zt+Zw -> Zw=Zt -> r = 0. The long answer is left for a new Phils'Lab video ;)

[@PhilsLab]

Thank you very much, Helge! Yes, as Kopiko already hinted at, it's a bit of a longer explanation but I'll be sure to make a video on that. In essence, you get reflections when you don't have properly terminated lines (anywhere between open and short), where these reflections will interfere (add/subtract) with your 'original' signal. Proper termination makes sure there are 'no' reflections.

[@olsif]

Minor mistake at 13:25 - the critical lengths for microstrip (outer layer) and stripline (inner layer) are swapped. Stripline should have the lower critical length (35mm). The takeaway that it's usually better to route high speed signals as stripline is sound, but not because of a longer critical length. Love your videos, really appreciate what you're putting together here.

[@DeShark88]

Apologies for resurrecting this. It's clear from the difference between dielectric constant (vs effective) that you're correct. However could you clarify why the takeaway is still correct? If signal integrity is all you care about (and not EMI), then is that still true?

[@dzidmail]

​​@@DeShark88Inner layer traces can also be thinner for the same impedance, so they take less space. (Especially true for differential pairs, where space between them will be allowed to be smaller too.) Also, since fields are better contained it's not only better for the emi but also for SI of nearby traces.

[@TheNewKill1212]

When using JLCPCB stackup, use their calculator as it gives slightly different values. Always check if your manufacturer provides impedance calculator.

[@rick_er2481]

Awesome information, once again!

[@PhilsLab]

Thank you, Rick!

[@rallymax2]

Yes, I did learn a ton of things!

[@Dennis-hb8tw]

Thank you, so informative! What left me puzzeling is, why a slow rise/fall time leads to higher frequencies. Turns out, it is again just Fourier transformation. That leads me to my question to you: Is it a thing in digital signals technology/research to not use rectangular/trapezoidal pulses, but others such as chirped (frequency modulated) pulses? This could increase data density and/or reduce loss/problems due too high frequencies. (Questions might sound strange, that is because I'm coming from a physics background and having no clue about electronics).

[@jvm8120]

Great content thanks

[@PhilsLab]

Thanks!

[@Vtrontv]

Thank you!

[@PhilsLab]

Thanks for watching!

[@kiprof4350]

Nice Video Thank you Phil!!!!

[@PhilsLab]

Thanks for watching :)

[@myetis1990]

these jellybean countermeasures are great. nobody talks about using can- shields , when to use, how to apply etc. a video about it would be great

[@gmendes1831]

Thanks for share :O)

[@cornevanzyl5880]

Would have loved to see a demo on the scope

[@biswajit681]

@phill would you add Signal Integrity and power integrity in your upcoming High speed board design course?

[@ricardomarques1769]

Great material resource!! Your content have been helping me to understand a lot about SI/EMI, how to design boards for EMI. I appreciate the work you have been doing to release such rich content. As per your recommendation I watched part of the Rick Hartley video and it was quite enlightening. I do have a question regarding 2 layer boards, what is the benefits of using 2 layer boards nowadays?? Since most circuits are distributed length (rise/fall times smaller than propagation time), wich can create a SI/EMI problems if not carefully routed. The fact that on most 2 layer boards you can only have one " solid reference plane ", usually on the 2nd layer, since most of the times signal is routed on 1st layer, and having a plane in the signal layer can actually increase crosstalk between interconnects. Most of the times is harder to achieve desired characteristic impedance on a 2 layer board, which in most cases require a wider transmission line, lol. So in the end, what is the benefits of using 2 layer boards ? You can get 4 layer boards for the same price and achieve desired impedance easily.

[@cian.horgan]

(disclaimer: very much not an expert) I think it actually is price in the end. On JLC's homepage at least 1&2 layer are $2/5 for 100x100mm, and 3&4 layer are $2/5 as well but only for 50x50mm, so 4 times the area for 2 layer. I think it might also be for time cost, and as a learning tool to illustrate fundamentals. It might be faster to design a 2 layer, or easier to automate or do on autopilot, and in the scale of a project with 40c PCBs I think the work hours are a much higher cost. Again, not expert, could be way off and it's actually easier for most people to work in 4 layers

[@dzidmail]

It's still cheaper, faster, more options (colors etc) to use 2 layer boards. If you are connecting cables to the board, ask yourself do they have a reference plane? No - so why 4 layer board then. Of course routing is easier on 4 layer.

[@leifefrancisco7316]

I really like this channel and I'm only 3 minutes into this video.

[@PhilsLab]

Thank you!

[@nayeemnnishi]

Hey Phil, was wondering do you have a video on pcb design rules for CE certification.

[@user-ww2lc1yo9c]

When a PCB contains a digital and an analogue portion we need to keep the noise from switching activity in the digital portion away from the analogue portion. In this case, I have read in a few places that the GND plane should be split. The two ground planes need to be connected only at a single point. Here I have read that it should be connected using an inductor so high frequency noise does not couple but at other places it has been that they can be connected using resistor. I do not know which is the right way. However, here you have said that the GND plane simply must not be split. Well, what then about PCBs that are mixed signal?

[@user-ww2lc1yo9c]

Have you made a video specifically on the topic of power integrity and PDN?

[@JeffGeerling]

17:18 - heh, and yet, many lazier designs just leave the gap and hope for the best.

[@antiprosynthesis]

Is it at all ever considered to low-pass filter these square-ish signals down to their fundamental frequency (so essentially down to a sine wave)?. Counterpoints I can think of are the need for extra components/traces on the board, and possible issues with signal delay due to the filter's phase response (which could potentially be compensated for in some way though).

[@danblankenship5744]

Do you have a video showing how to minimize EMI using bypass capacitors (SPI SCLK, CS, & MOSI)? I am attempting to correct a design error from previous engineers where they added 1nF decoupling capacitors to the SPI signals slave ADC ICs. It seemed to work until a new configuration required removing one of the slaves. This is causing erratic communication issues. I found these engineers added these capacitors to combat EMI. I need information about adding large capacitors as a viable alternative.

[@cian.horgan]

Hi I had a question brewing while watching your recently public udemy design video and it came up again here; You mention never having a signal cross a break in the ground plane, but am I right in saying you did cross it a few times in the STM udemy design? I'm referring to the necessary bias to run very short traces on the bottom layer, I think there one in routing the USB connector for example. Does that not introduce a small cutout below the USB signal return path? I may have the wrong end of the stick or it might just be a necessary compromise for 2 layer boards. Also very much enjoyed the video, I'm an EE undergrad that has zero PCB courses in my program and I had just watched the Altium grounding video a few days ago. This is a very helpful summary and application of some of it

[@EfraAv]

Great video with tons of useful information as always! Thank you Phil Is the stackup: "Signal / GND / GND+Power tracks / Signal" better than "Signal / GND / Power/ Signal"?

[@PhilsLab]

Thank you, Efrain! I typically would go with Sig/GND/GND/Sig, with routed power on the signal layers. Definitely wouldn't split up the GND planes with power tracks.

[@EfraAv]

@@PhilsLab thanks for your reply. So, between "SIG /GND /GND + ROUTED PWR/SIG" vs "SIG/GND/PWR/SIG" which one would be better?

[@semihboyno]

Hello Phil, thank you for yet another great tutorial. I have a question regarding the ramp times. According to IBIS model [Ramp] section rise and fall values are specified by 2 values. For example, dV = 2.14V and dt_f = 0.76ns. Their ratio gives the slope of the ramp. Should these values not be scaled for 90-10% of total of 3.3V? i.e. According to dV/dt_f = 2.14V/0.76ns, ramp value is 2.82V/ns. Scaling this for (90%-10%) * 3.3V = 2.64V would give a result of 0.936ns.

[@spruce1000]

I think I missed something about the dv/dt percentage range from the IBIS model. Why is that? What are we converting here?

[@smartups1]

can you make a video on same type this EMI effect on microcontroller and spwm Sine wave inverter.

[@remy-]

Is there a reason why you terminated the signal traces on your em board with 1k resistors, would it be interesting to end them with sma connectors for oscilloscope measurement?

[@giovannimezzina2849]

Hi Phil, I think there is an error at min 13:54. If eps = eps_eff should be used for outer layer, the l_crit_out is ~41 mm, while the l_crit_in must be 35 mm. So inner layer is more critical in terms of length. Where is the truth ? :) Thanks a lot for the video !

[@cheolhongan3470]

Where can I purchase the board? I searched JLCPCB but I couldn't find it? Can you give more information? Thank you for great work.

[@akhilab9715]

Hiw much time u took to design that zynq board

[@Ritzz45]

Love these videos as always, will you be releasing any more paid content in the form of courses? I signed up to the one you have on udemy but I'm greedy for more knowledge.

[@PhilsLab]

Thank you! I'll be releasing a 'Practical Digital Signal Processing' and 'Advanced Hardware Design' course sometime within the next year!

[@TomasApolonia]

What I'm hearing is that I need at least a 500MHz oscilloscope to troubleshoot 36MHz MCUs :)

[@Karlemilstorm]

I'm wondering why you have put vias all around the border of the PCB you showed of in the design. Is it in order to contain the fields from escaping from the sides of the board? When is it necessary to do so and how much does it help reduce EMI?

[@dzidmail]

I dont think it matters much for the emi from the traces (their fields are very narrow anyway) but rather to stop planes themselves emitting when their voltage bounces slightly when driving fast slope ICs. Decoupling caps and planes capacitance should stop this anyway, but no one would want needs a risk.

[@user-ww2lc1yo9c]

The PCB mentioned in this video that can be used to learn about signal integrity stuff, where are the files for it?

[@riskable]

Something that's not really obvious in the video that I have a question about, specific to the section about vias: Would pairing a signal via (that's going from the top layer of the board to the bottom layer or vice versa) with a ground via reduce "voltage wobble" on nearby analog tracks? I have an analog keyboard design that has WS2812B LEDs where the output signal of the LEDs crosses over the analog signals from the hall effect sensors (perpendicular) in a lot of places and vias are basically "free" so it'd be no big deal to put them all over the damned place. Obviously, a multi-layer board with layers dedicated for digital and analog signals would be ideal but I don't have that kind of money 😁. Also, I'm able to work around any and all voltage wobble in the firmware but reducing it makes that job a *lot* easier and also would enable finer resolution in the detection of keydown events. I'd also be curious to know if having a ground pour of the power plane helps or hurts voltage wobble/noise in the analog signals. Right now I've got a ground pour on the bottom (that necessarily gets broken up in very short bits here and there) and a copper pour for the 3.3V analog power on the top but that top copper pour is broken up all over the place but there's no islands--there's continuity throughout. I'm not sure what sort of impact that would have on things.

[@robiniddon7582]

The top layer 3v3 pour is not a good idea. Route it as a signal, point to point. Where you have broken the ground plane and you have signals crossing that break, the best you can do is to put GND 'patch' links across the break on layer 1. Your return will now flip to L1, run parallel to the signal is returning across the break, then return to L2. If it's an analog signal I would try to put GND patch in pairs around the signal only where it crosses a break, though of course valid to route signal+GND as a pair from source to sink.

[@riskable]

@@robiniddon7582 Why is the top layer 3v3 pour not a good idea? Should I just not have a top layer pour or should it be GND?

[@billyjoe3309]

Your knowledge is super impressive, been following you for a long while now, love the vids! Is it okay to do: Layer1: GND with 3.3V and 5V traces Layer 2: N/A with signal traces only Layer 3: N/A with signal traces only Layer 4: GND with 3.3V and 5V traces

[@PhilsLab]

Thank you very much! No, I'd rather recommend L1: GND, L2: Sig/PWR, L3:Sig/PWR, L4:GND. There's enough spacing due to the thick core between L2 and L3 that in this case it's okay to have adjacent signal layers.

[@billyjoe3309]

@@PhilsLab Ahh so power can be the same layer as the signals them, and because we have GND on L1 and L4, it sort of protects it all? I'm an by no means an expert, but I do love PCB design and electronics. Thanks so much for taking the time to reply me!

[@cian.horgan]

@@billyjoe3309 @Billy Joe also not an expert but in the video he does briefly address this; saying that it's usually preferable to route your power. In this case that means power traces in the "signal" plane. As I understand it, the potential for slightly less optimal coupling is outweighed by having a solid(ish) ground plane for return paths and shielding. 10:26

[@douggale5962]

I thought the edge bandwidth formula was 1 / (2 * pi * risetime), so 1ns gives 159MHz? Is that wrong?

[@ebrahimsalem7607]

Make mixed design hardware course by using altium

[@AnimaMaestro]

Love your videos !! I was wondering what approach you recommend regarding clocks. Especially when devices have their own internal oscillator or can take external crystal or clock signals. I'm working on a design where I have 6 devices that have internal clocks (1 MCU running at 120MHz from internal 8MHz + 5 devices running from internal 12Mhz). Plus one other device requiring external 24MHz (from crystal or clock). My current plan is to use one single 8MHz oscillator to feed the MCU which has the ability to generate external clocks so I would generate the 12 and 24MHz clocks and distribute from this central location. Is this a good approch ? Or is it better to let every device use their internal clock ?

[@user-ww2lc1yo9c]

I am completely taken by surprised that the pregreg and core are different things, I think that there is core between each pair of copper layers. Now, I am very confused.

[@spanksy_]

First! Edit: Are there still plans to upload a GitHub repository for the DSP FX pedal firmware?