PVT Analysis of CNTFET STI Inverter in Cadence.

[@shreyanshujaiswal204]

great explanation

[@dr.hariprasadnaikbhattu]

Thanks and Welcome

[@shreyanshujaiswal204]

@@dr.hariprasadnaikbhattu Sir if we make any changes in verilog A code , like if we replace 32 nm to 45nm then will it be reflected to all the circuits which were made on 32nm ?

[@byreddyvenkateswarareddy8573]

Nice explanation,

[@dr.hariprasadnaikbhattu]

Thanks for the Appreciation. What is that can we tool

[@byreddyvenkateswarareddy8573]

@@dr.hariprasadnaikbhattu Can we get digital design explanation in tool

[@suchithareddy953]

Good morning sir. Sir can you please do a vedio on how to import GNRFET model into cadence sir

[@dr.hariprasadnaikbhattu]

Hi, GNRFET Verilog-A model is not available. Spice model exist. Difficult in cadence

[@martinnjoroge6006]

Greetings sir. Which virtuoso version is this? I am starting in vlsi design and there are very many versions of virtuoso I don't know which to start with

[@dr.hariprasadnaikbhattu]

Hi, Cadence will not change with any Versions. It remain same only new updates are added.

[@suchithareddy953]

Good morning sir. Can you do an vedii on how to download and install HSPICE in to PC

[@dr.hariprasadnaikbhattu]

Hi, HSPICE is not free it is commercial.

[@suchithareddy953]

Hello sir. If possible can you do an vedio about radiation hardened sram. How to overcome single event upset in sram

[@dr.hariprasadnaikbhattu]

Hi not much information on the topic right now. I will check

[@suchithareddy953]

Thank you sir

[@suchithareddy953]

Sir, CNTFETS have no effect on temperature sir. Is it correct

[@suchithareddy953]

I mean is it applicable for all the circuits made using cntfet

[@dr.hariprasadnaikbhattu]

Yes, the temperature effect is not there on cntfets.

[@suchithareddy953]

@@dr.hariprasadnaikbhattu thank you

[@dr.hariprasadnaikbhattu]

@@suchithareddy953 welcome