RAM and ROM design in Verilog | Verilog Project | EDA Playground

[@ArjunNarula1122]

Please find the code in the link description. Any suggestions or queries are most welcomed. PLEASE SUBSCRIBE TO THE CHANNEL. Let's aim for 400 SUBSCRIBERS!! Other Projects- ►Traffic Light Controller in Verilog - kzbin.info/www/bejne/j6Wan6Jsp9x2jM0 ►Round Robin Arbiter in Verilog - kzbin.info/www/bejne/jmfSe6Ftp55gbtU ►Vedic Multiplier in Verilog - kzbin.info/www/bejne/bH6Wn6yvhsujfrc ►Clock with Alarm in Verilog - kzbin.info/www/bejne/poXOYntrZcprmKs ►Washing Machine in Verilog - kzbin.info/www/bejne/n3LSmmygid-rmas ►N bit Multiplier in Verilog - kzbin.info/www/bejne/op7ddJeua8yemrc ►PWM Shift Register in Verilog - kzbin.info/www/bejne/hqucpIOcobCjjsU ►Vending Machine in Verilog - kzbin.info/www/bejne/qnvGYZWid6mFsNE ►Hexadecimal Keypad Scanner in Verilog - kzbin.info/www/bejne/j2LGoWWhrNSma68 ►RAM - ROM Design in Verilog - kzbin.info/www/bejne/o2Kbiohvrc94irc

[@divyechopra]

Great job Kush!

[@ArjunNarula1122]

Indeed excellent work ,Kushagra !!! Thank you for watching the video!!!

[@yuganshibharti3892]

Very intersting topic. Amazing work done by Kushagra and Arjun 🔥💥

[@ArjunNarula1122]

Thank you Yuganshi 😊😊

[@yatharthjain00]

Compelling presentation kush!🔥💯

[@ArjunNarula1122]

Indeed , great work Kushagra ✨ Thanks for watching the video Yatharth ✨

[@varunbansal2633]

Great work Kushagra and Arjun 🔥🔥

[@ArjunNarula1122]

Thanks Varun ✨✨

[@Rkshorts0707]

Well explained I was facing difficulty to understand to this but after watching this video it helped me a lot to understand in a better and easy way ....... 😀😀

[@ArjunNarula1122]

Glad you liked the video!!

[@ishajain949]

Superb explanation and a great project Kushagra ✨

[@ArjunNarula1122]

Indeed great work by Kushagra✨

[@diwanshi6669]

Great project with superb explanation👍

[@ArjunNarula1122]

Thanks for watching ✨😊

[@yuktasachdeva7822]

Good topic for a Project & well explained 👏👏👏

[@ArjunNarula1122]

Thanks for watching the video ☺️

[@harmansaini9481]

Great work guys!🙌🔥

[@ArjunNarula1122]

Thanks for watching Harman✨✨

[@Desi_Odyssey]

Excellent job guys keep up the good work 👏

[@ArjunNarula1122]

Thanks Anushi di ✨✨

[@saksham2031]

Unique idea and well explained 💥

[@ArjunNarula1122]

Thanks a lot for watching ✨😊

[@saikashyap4151]

Great Content Bro!! Please continue making videos!! Will help many!!

[@Weekend_vloger_yt]

Great project guys... Well done... 🔥🔥🔥

[@ArjunNarula1122]

Glad you liked it Anshul ✨

[@arshiyagarg9882]

Great project with great explanation ✨✨

[@ArjunNarula1122]

Thanks for watching Arshiya ✨✨

[@sarthakwali1210]

Informative Project 👍

[@ArjunNarula1122]

Thanks for giving it your time, Sarthak!!

[@adityamehta4147]

Well done, Quite helpful👍🏻💯

[@ArjunNarula1122]

Glad you liked it ☺️

[@mehakgoyal7173]

Very well explained 🔥🔥

[@ArjunNarula1122]

Thanks for watching ✨✨

[@chayanbatra8410]

Great work guys👍

[@ArjunNarula1122]

Thank you ☺️

[@atushgoel7823]

Superb Video very well explained

[@ArjunNarula1122]

Thanks for watching ✨

[@vimminarula5523]

Nice presentation God bless you

[@yuktasachdeva1204]

Bring it on 🥳

[@ArjunNarula1122]

Hope you like it!!

[@yuktasachdeva7822]

@@ArjunNarula1122 Yes I do 💫

[@ArjunNarula1122]

@@yuktasachdeva7822 😇😇

[@arunavasamanta3045]

I thing addr_reg is not required for single port RAM also.....doing q = ram[add_reg]; in L19 and commenting L22 will work properly.

[@shaikmahammadhussain2752]

Yes😅😅😅

[@saumyachandra3553]

Great work guys 👏 👍

[@ArjunNarula1122]

Thanks 😊

[@quotes8508]

Nicely explained 👍🏻

[@ArjunNarula1122]

Thanks for watching ✨✨

[@raeleenkanda8270]

Going great 🌟🌟

[@ArjunNarula1122]

Thanks Raeleen ✨✨

[@adityaagrawal8717]

Awesome work

[@ArjunNarula1122]

Thanks 😊

[@divyechopra]

Nice video!!!

[@ArjunNarula1122]

Thanks!!

[@patilxvikas]

Great project 👍

[@ArjunNarula1122]

Thanks for watching ✨

[@prakharawasthi1419]

thanks brother for descibe it in very simple manner.

[@ritikgupta8478]

Nice project🔥

[@ArjunNarula1122]

Thanks 😊

[@aryankr]

Thank you very much. Great explanation

[@vanshikamahendra7879]

Hello I came across your youtube channel, I had a query regarding eda playground; is it some how possible to design block diagram in it?

[@heyitsmea8883]

Why is address bit is 6? I didn’t get. Can u elaborate please

[@rachanaparekh7915]

Great work! Great playlist! Had a query tho, have you worked with lookup tables? I needed some guidance regarding implementing one for my project. Thanks :)

[@kavanakrishna3787]

Bro, can you please help me with the verilog code for 64KX 8 Rom???

[@abhijeetchauhan9132]

hii sir I want to reaserch paper for design dual port ram in verilog please provide me

[@shafeeqahamed3669]

is this a static DPRAM ??

[@vimminarula5523]

Excellent

[@ArjunNarula1122]

Thanks mumma ✨

[@loveff9172]

thank you so much💗

[@andrewlipase6554]

nice

[@ArjunNarula1122]

Thanks a lott😇😇

[@harmanchawla33]

💯💯

[@ArjunNarula1122]

😇😇

[@sarthakchoudhury5237]

Can we add these projects in our resume at btech level

[@vishalgowtham896]

Thank you , great explanation .