Reset Domain Crossing Technique | RDC Technique | How to fix RDC Violation | VLSI Interview Question

[@Electronicspedia]

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[@saikumardussa1643]

Nice explanation sir it wil help for lots of people Keep going 🥳

[@Electronicspedia]

Thank you 🙂

[@MidhunSasikumarpanangat]

may i suggest that you should add reset isolation techniques to the list of RTL methods. its a commonly used method

[@lakshmi-kb4ww]

Thank you good explanation

[@akshaykumarmane1527]

its very useful. please provide something on power domain crossing

[@Rajat0607]

Thank you for your videos. They are amazing Can you pls tell us more about your professional background ?

[@Electronicspedia]

Please take a look into Electronicspedia about page.

[@manpreetkaurjaswal1175]

why is the double synchronizer out in Reset domain 2; shouldn't we send synchronised output from domain1 itself?

[@user-qs9wg3dn3g]

Thanks sir, its very helpful. please provide us with docs/pdfs , if available, so that we can revise the things.

[@manpreetkaurjaswal1175]

what would happen in case of synchroniser fix if rstn2 signal changes while we are recieveing data in synchroniser from reset domain 1

[@azrsn5596]

Nice video though i do have a few of comments: 1. Fix #1 "RTL fix" is risky advice as it will not work for a multibit signal. If you a multibit signal RDC we must treat it as asynchrous from the destination side and synchronize it with one if the known CDC methods (e.g asynchronous FIFO...). 2. Isn't fix #3 also technically an RTL fix? 3. fix #4 is not a fix. rather constraints are a necessary step of reset ordering. waivers of course don't fix anything either.

[@Electronicspedia]

Hi, your comments are all valid and i completely agree. Fix 4 is not really a fix, it's more of a waiver through review. And it should be used only when design is right by architecture and reset ordering is done in the right order. .

[@RandomHubbb]

2nd case is very confusing, i think it is a bad example to begin with. why would someone assert reset in domain 1 but then deassert reset in domain 2. what kind of functional use case is that to begin with?

[@chessten]

Hi, for the RTL fix technique, instead of double synchronizer, can it be just 1 flop? Since the destination flop can act as the 2nd stage synchronizer itself?

[@Electronicspedia]

Hi, Regular Flops should not be used as synchronizers, because in placement and route these regular Flops might get placed at far distances, which decreases MTBF, hence leads to failure. Instead we always use synchronizers which are standard cell components that's why we have synchronizer and then flop in destination.

[@chessten]

@@Electronicspedia ahh, thanks.

[@ashishpudi4]

@@Electronicspedia we need to give same clock what we given in flop1 to Double flop synchronizer ? and rstn2 is deasserted during that time as well ?

[@Electronicspedia]

Yes same clock for both flops.

[@user-he1gf2ix4b]

Sir what to do if we have to apply clock domain crossing and reset domain crossing together?

[@Sachindeo93]

Is double synchronizer similar to two F/F synchronizer used for CDC?

[@Electronicspedia]

Yes, double synchronizers and Two stage synchronizers are the same.

[@Sachindeo93]

@@Electronicspedia Btw thank you for such an excellent explanation. You have explained such a difficult to grasp concept in such a simplified manner!

[@Electronicspedia]

Thanks for the compliment 😊

[@chaitanyap7502]

Anna naanu nimma nodidini, haage maathanadidini... neevu Lantiq nalli kelasa maadidira ?

[@Electronicspedia]

No, I was in Intel and now in Qcom

[@nehabarothiya3527]

If we have different clock domains as well with different reset domains. How to fix it

[@Electronicspedia]

If we have different clock domains and reset domain then we may to include synchronizers and also we need to solve the issue with reset ordering.

[@RanjanSingh-pm6ze]

sir how we will know that reset one is asserted and now gated clock should be turn on. AS you have explained that when reset1 will de-asserted gated clock of second flop will be off, and when reset1 will be asserted then gated clock will be on. so how we will know that weather it is asserted or not?

[@Electronicspedia]

Hi Usually system resets will be software controlled, so you know when the reset is going to assert or deassert. If some resets do not have software override and if they are completely hardware based then you might get info from FSM state and/or you can add simple edge detection logic to check whether reset is asserted or not.