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Пікірлер
@srcreations8895
@srcreations8895 6 күн бұрын
Hello sir, can I know what are the qualifications you have to teach this concept
@AkashSingh-dd2te
@AkashSingh-dd2te 6 күн бұрын
RDC Issue is basically source reset to destination clock issue. It is related to reset assertion which means that if reset of source flop gets asserted and it causes input signal to destination flop change during aperture window of destination flop then that flop goes into metastability. The point here you are making is reset de assertion. Here, What happens is that if reset gets deasserted in the recovery - removal window of the flop, then it will cause metastability, which further means during that window period, reset signal should be stable. Yes, It can also cause destination flop goes into metastable state but It will be not be treated as RDC issue. This will be another form of CDC only. It can be taken using reset synchronization using reset synchronizers.
@Electronicspedia
@Electronicspedia 6 күн бұрын
Agree to your points.
@Electronicspedia
@Electronicspedia 6 күн бұрын
I have explained your points in the next video .
@mbreakn2620
@mbreakn2620 9 күн бұрын
Not bad. Nice job!
@MidhunSasikumarpanangat
@MidhunSasikumarpanangat 12 күн бұрын
may i suggest that you should add reset isolation techniques to the list of RTL methods. its a commonly used method
@travelfreakphani5933
@travelfreakphani5933 Ай бұрын
thanks sir !
@yarajanasaisindhuja5482
@yarajanasaisindhuja5482 Ай бұрын
Kudos to your efforts! 😊
@manpreetkaurjaswal1175
@manpreetkaurjaswal1175 Ай бұрын
what would happen in case of synchroniser fix if rstn2 signal changes while we are recieveing data in synchroniser from reset domain 1
@manpreetkaurjaswal1175
@manpreetkaurjaswal1175 Ай бұрын
why is the double synchronizer out in Reset domain 2; shouldn't we send synchronised output from domain1 itself?
@Vidyashreers
@Vidyashreers 2 ай бұрын
Great explanation!!
@bsrinivasarao8622
@bsrinivasarao8622 2 ай бұрын
LATCH WILL HAVE INPUT AS CLOCK ?? IS IT CORRECT ?
@Electronicspedia
@Electronicspedia 2 ай бұрын
Latch will not have clock pin, it will have enable pin. But we are connecting clock to enable pin.
@bsrinivasarao8622
@bsrinivasarao8622 2 ай бұрын
IS IT D LATCH OR D FF , AND WHERE IS THE INPUT FOR D LATCH , U HAVE APPLIED ENABLE AND CLOCLK TO ANOTHER INPUT , THEN HOW TO AND WHERE WE CAN APPLY INPUT????
@Anithachintala
@Anithachintala 2 ай бұрын
Hi sir, you mentioned we will add 1 once pointers reaches to 7th location we compare MSB bits. Lets consider my both pointers are rolled overed onve so their msbs are 1 and if write pointer again reached to 7th location and read pointer is still at 0th location now when we compare msbs even if we add 1 to write pointer it will be still 1 and read pointer is also having 1 as msb due to previous full condition. Please clariy sir how to compare full condition in this case
@kamalapurammaheswar2854
@kamalapurammaheswar2854 2 ай бұрын
is it possible to add half empty / hall full condition. if so how can we add that particular condition.
@sailakhaz8350
@sailakhaz8350 2 ай бұрын
sir i have a doubt that the same binary to gray could be applied to the synchronous fifo or not
@Electronicspedia
@Electronicspedia 2 ай бұрын
For synchronous fifo there is no need to convert from binary to gray
@user-oo8vi5cf1x
@user-oo8vi5cf1x 2 ай бұрын
Thank you ❤
@sanskritisawant6161
@sanskritisawant6161 3 ай бұрын
can someone help solve this question? FIFO DEPTH? Given Rules: i) A is input data and B is output data ii) frequency(clk_A) = frequency(clk_B) / 4 iii) period(en_B) = period(clk_A) * 100 iv) duty_cycle(en_B) = 25%
@Awakened_Pot
@Awakened_Pot Ай бұрын
Found this in some book :) This can be solved by taking an example. Let the frequency of clk_B be 100MHz. That implies, frequency of clk_A = clk_B/4 = 25MHz Period of en_B = (1/25M) * 100 = 4 s As duty cycle of en_B is 25%, it will be high for a duration of 1 s. That means B receives the data for 1 s and will be idle for 3 s. Where as A sends the data every 0.04 s. So in 4 s it can transmit 100 words. And B receives 25 only, so we need to store the rest of 75 words in the FIFO. So the minimum size of FIFO required is 75 words.
@sanskritisawant6161
@sanskritisawant6161 Ай бұрын
@@Awakened_Pot Thank you!
@user-lq9dh7dp6p
@user-lq9dh7dp6p 3 ай бұрын
Thank you
@Yen-TingChen
@Yen-TingChen 3 ай бұрын
my hero
@pallakishoreyadav4537
@pallakishoreyadav4537 3 ай бұрын
sir once the data enters metastable state it can settle to any value how can we ensure that we are sampling correct data at the 2nd flop
@shubhamshahi6280
@shubhamshahi6280 3 ай бұрын
No clearity ,I am still confused.
@mejaeuk1104
@mejaeuk1104 3 ай бұрын
감사합니다. Thank you!
@RandomHubbb
@RandomHubbb 4 ай бұрын
not only deassertion! rstn1 could also assert at a point close to clock edge and flop2 can have metastability due do data change to 0 close to edge
@avvarutheja
@avvarutheja 3 ай бұрын
Yes, this is the major problem. it happens only when aserting the rstn1. Hence some RDC checks are formed to make sure they are destination flop is protected from asyncronously resetting the source flop.
@Platica.Vasile
@Platica.Vasile 4 ай бұрын
Thank you for the quick video, but for a more thoroughly you should corelate this with a timer to see exactly how the timescale affects the program.
@abdullahjhatial2614
@abdullahjhatial2614 4 ай бұрын
what is difference between two flip flop and std double synchronizer ? they look similar in ciruit
@smitpatel7700
@smitpatel7700 4 ай бұрын
awesome explanation!
@smitpatel7700
@smitpatel7700 4 ай бұрын
can we add and gate to gate-off ren also ? like done on WR side?
@RandomHubbb
@RandomHubbb 4 ай бұрын
2nd case is very confusing, i think it is a bad example to begin with. why would someone assert reset in domain 1 but then deassert reset in domain 2. what kind of functional use case is that to begin with?
@Shahidsoc
@Shahidsoc 4 ай бұрын
light is in ur back, so shade come on board
@shreyagupta5742
@shreyagupta5742 5 ай бұрын
Very well explained! Thank you
@Yemo_naniartsanddanc396
@Yemo_naniartsanddanc396 5 ай бұрын
Good explanation🎉
@danielarthur7739
@danielarthur7739 5 ай бұрын
I have a question, Im using clock gating in my design. My question is: the clock gating should affect the dual flop synchronizer or the synchronizer must have the free clock always?
@rohanyadala9096
@rohanyadala9096 6 ай бұрын
Super..
@ytaccount9420
@ytaccount9420 6 ай бұрын
For fast to slow, using toggle sync solution, how do we calculate the min cycles to be allowed before we can safely detect next pulse? Is it 4 (toggle ff- 1, double sync -2, d ff -1)? But toggle ff is triggered by clkA, so kinda confused How to calculate safe frequency of pulse
@kpark5467
@kpark5467 6 ай бұрын
Nice explanation, Thank you. How do you set SDC constraints for CDC on 1st_flop and 2nd_flp ? and what else SDC do I need to set ?
@user-he1gf2ix4b
@user-he1gf2ix4b 6 ай бұрын
Sir what to do if we have to apply clock domain crossing and reset domain crossing together?
@docvedios1955
@docvedios1955 6 ай бұрын
Simply outstanding, got perfect picture on the topic. Thanks a lot
@ahyungrocks5509
@ahyungrocks5509 6 ай бұрын
Great easy to follow series!
@bhargavchiru6002
@bhargavchiru6002 7 ай бұрын
what have you studied ?
@nenadmilutinovic4752
@nenadmilutinovic4752 7 ай бұрын
Hello Sir, what will 15.5 be rounded off to? 16 or 15? Thank you in advance!
@harshitha-8256
@harshitha-8256 7 ай бұрын
I found the video extremely useful for my interview preparation, Thank you!
@akshaykumarmane1527
@akshaykumarmane1527 7 ай бұрын
its very useful. please provide something on power domain crossing
@bhavana_kitchen
@bhavana_kitchen 8 ай бұрын
for the double synch of the ack signal the clock used is clka?
@user-xy5sd8my2e
@user-xy5sd8my2e 8 ай бұрын
thanks bro! that's very clear. Btw, did you post setup time and hold time video?
@starlightsr
@starlightsr 8 ай бұрын
Can you elaborate on the fifo full condition w.r.t rollover? Also, should the RHS of the equation be rd_ptr_sync[3:0] for fifo full detection?
@yasyas7740
@yasyas7740 8 күн бұрын
Same question
@devchadha
@devchadha 8 ай бұрын
Awesome explanation! Have you posted the video with the solution to the problem you have discussed at the end of the video? Could you please share some references to study about the problem.
@user-qs9wg3dn3g
@user-qs9wg3dn3g 8 ай бұрын
Thanks sir, its very helpful. please provide us with docs/pdfs , if available, so that we can revise the things.
@SangNguyen-un8ni
@SangNguyen-un8ni 9 ай бұрын
In the STA nano book, I have seen a report that startpoint is UFF and endpoint is UAND. So when should we use ICG and when should we use only AND gates?
@chipking005
@chipking005 9 ай бұрын
Hi, Nice one. I've a question. Which is a best way for a DV engineer to verify the reset tree?
@surajkumar-no5et
@surajkumar-no5et 9 ай бұрын
may be glitch in this circuit b/c of unequal comb path delay .....?
@garrisongreenwood3144
@garrisongreenwood3144 9 ай бұрын
Not very good. Uses “push” and “pop” to describe FIFO read/write operations when these terms are associated with stack memory operations. Could be a source of confusion.