CMOS Inverter - DC characteristics/ Transfer characteristics

[@LakhanSingh-li8jd]

You Don't have any idea how difficult it was in class and how simple it is here It's like output form cut-off to saturation.😂 Thanks man

[@abc2001]

I had exams today afternoon from 2pm to 5pm and watched your entire VLSI playlist from morning 6am till 1pm. And dude almost half the paper come from your playlist! Love you Shree 😍

[@vikasbansal4180]

Superb Explaination sir, taking values makes it more easy and understandable. Thanks a lot

[@Arjun_Vasudevan]

I had a hard time with these in class.....thank you so much !!

[@paarthshah1629]

I'm still Gonna Fail

[@ashayadav7526]

Thanks I am watching it really clear concepts, loved it.

[@jahidchowdhurychoton865]

Excellent lecture. Thanks very much.

[@ShrenikJain]

Welcome 😃

[@AbidAli-mj8cu]

At 4th region higher boundary, its "Vdd - |Vtp|" not "Vdd +|Vtp|". anyways thanks for the video bro

[@NomadMaveric]

Nicely explained, Shrenik Thanks,

[@abhinawraj5749]

great video...took me no time to get the logic right

[@vijay6161]

Bro really really good and ur way of explanation is best❤️

[@ankit_yadav11]

yar aapne itna complex q bna diya is chij ko , thora easily handle kiijiye yar aur hindi me boliye request h aapse ,

[@ramsaivelidandi6777]

lecture was so good thanku

[@dharanidharan6978]

Love you brother❤️

[@misspriya22]

Thanku so much sir😊

[@KiruthigaKumaran-zh9kq]

Thanks a lot bro

[@MAHMUDURRAHMAN-pk6gm]

For case 3 how do you know that output is 2.5 volts?

[@ankit_yadav11]

yad karke aata hai ye log aur apne class ke students ko bolkr comment karwata hai

[@optimisticfacts3486]

Tq sir

[@maulanawahyudi7127]

Thankyou sir

[@maliharish3143]

Very Conceptual lecture.Thankyou

[@ShrenikJain]

welcome :) share this video with your friends too

[@rahuldesale9261]

Thenx 👍👌🙏

[@bommerakoushik3000]

can you hep me the transfer characteristics(Vgs against Ids)

[@eddr6124]

Kahin kahin bekaar hai....but hey great effort man, you just provided what I was looking for 😊

[@rameshpolisetty5519]

in case 4 ,for pmos if i take vin as 4.1(as u said ) it becomes cut off na but u said on how is it possible

[@ShrenikJain]

ramesh babui Polisetty Thanks for pointing out this part.. Vin should be less than or equal to 4. This should be the condition because when Vin is increasing towards 5v it is becoming ideal CMOS where pMos is cutoff region

[@rameshpolisetty5519]

Ur videos r very useful to me thank u somuch

[@ShrenikJain]

ramesh babui Polisetty Welcome 😃

[@Philly191233]

great vid thanks bro

[@ShrenikJain]

Welcome 😃

[@erbkgupta8679]

Thanks

[@ShrenikJain]

welcome :)

[@anilkumarpattapu4309]

Sir can u pls tell me how u saying linear or saturation by comparing voltages?

[@ShrenikJain]

Please watch basics of CMOS video lecture for this

[@anilkumarpattapu9107]

In case 1 vgs,p

[@anilkumarpattapu9107]

How sir can u reply me pls?

[@saianu7436]

@@ShrenikJain layout and stick diagram of cmos nand not gate

[@abhiram2760]

Tqqq

[@nad1ax2]

you're a messiah

[@prep_shots5063]

Too speed

[@sreeramdarsan463]

this is a great, but the way you pronounce "Volt" and provide extra emphasis on the "T" is so annoying