SPI Master in FPGA, VHDL Code Example

Here's the SPI Master core functionality written in VHDL for FPGA. This video I walk through the code so you can understand how it works.
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[@damny0utoobe]

I've been waiting a month for you to post this

[@Nandland]

Become a Patreon supporter! They have had access to this video for weeks.

[@krishnasai4698]

@ nandland, sir, you said serial clock frequency is half of the input frequency. Is there any specific rule for that? If any reference is there for that,. Could you please provide me

[@kothapallidorasaimanikanta1601]

Hey @nandland, which specification-based spi protocol has been followed for writing this VHDL code, could please let me know?

[@AswathyVVAchu]

Hai, Yours explanation in very good. Could you please provide SPI SLAVE code and simulation in VHDL

[@spoorthim.n.2537]

Please do something on AXI, timing constraints and TCL

[@bobesfanchi]

timing constraints please....

[@batuhanbulut8461]

hello ı couldnt understand why we don use any axı signal interface phonema

[@23foundation]

Thank you for video! I don't understand the detail... "o_TX_Ready" signal declaration as output, but this signal use in MOSI_Data and MISO_Data processes as read. How it works?

[@Nandland]

Just because a signal is label as an output with "o_", it can still be used internally.

[@samedgonul4149]

@@Nandland slave takes clock from master so do we need to give same clock name both for master and slave? and there is only one clock for both slave and master , right?

[@chinhanbuile5389]

can you help me fix this error: "Object o_TX_Ready of mode OUT can not be read."

[@Nandland]

You can't read an output in Verilog unless it's of type reg. e.g. output reg o_TX_Ready. Another solution is to create an intermediate register r_TX_Ready and assign o_TX_Ready = r_TX_Ready, then you can use r_TX_Ready wherever you like.

[@kyrinky]

For future reference, for that part to work you'd have to switch Vivado ( or whatever you use) to VHDL 2008. VHDL is not able to support that.

[@abhisheksingh-db4kk]

Sir Can you explain token ring protocol in your next video lecture

[@Zapho300]

What's your preference, VHDL or Verilog?

[@Nandland]

If only someone created a video on just that subject. Oh wait! kzbin.info/www/bejne/q6fUhYWedryca5o

[@shri__can]

I'm a little confused here. Why is the MOSI signal (i_TX_Byte) an input for the entity SPI_Master? Shouldn't it be an output (Master OUT)? Similarly why is the o_RX_Byte an output when it is Master IN?

[@kyrinky]

@@julianpeterpollak7219 Thanks Julian, that clarified things for me.

[@tombola9445]

Ordinarily I do really enjoy your vt' however, some of your coding styles confuse me. That is, why use asynchronous resets, and why use not just use a state machine (more logic but infinitely more readable) also you like to use concurrent signal assignments rather than clocked processes. I only ask as most day jobs require SIL or do254 and these coding styles wouldn't pass a code review. Sorry to be a downer, but I've picked up a few handy tips from you, but I find my disagreeing with some of this.

[@xgh1000]

I agree with you, but can't seem to wrap my head around programming the SPI with state machine... Would you mind terribly helping me?