SPI Master in FPGA, VHDL Testbench

Now we introduce the testbench for the SPI Master in VHDL. The testbench is critical to ensure our code is working in a simulation environment.
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Also get yourself an FPGA board, The Go Board, so you can try this code on your own.
www.nandland.com/goboard/intr...

[@user-sj9st7xc3c]

You are awesome 😎 This online website for coding just saved my life 💜❤️

[@nitdawg007]

Ignore my previous comment I figured it out and it works.

[@nitdawg007]

Thanks. This a great resourse to learn VHDL. I was trying out a simple OR gate example with free account but run was clicked it said a do file was created but the simulation never appeared.

[@AkbarRajaei]

Do you use Vunit or UVVM/OSVVM ? Whether yes or not, please share your opinion.

[@babatundetaiwo2817]

What does initializing a signal do in hardware? do the initialization add to the synthesis performed by the EDA tool?

[@mashur7835]

I have an fpga with 27MHz clock. Can I use both the pos edge and neg edge to create a 54Mhz sclk signal for the spi slave?

[@shashi3758]

hey russel thanks for the video .. but there is some problem in this code I'm not able to run synthesis in vivado 2018.3 ... can u please check it out ...

[@euxheniodragoj2806]

std_logic_vector is missing "(7 downto 0)" in a couple of places if you downloaded the code from GitHub. Compare it with the video, look for "i_TX_Byte" and "o_RX_Byte". Help yourself with this: www.edaplayground.com/x/5CMQ Also the "to_hstring" explicit cast was not working for me, in the report statements, at the end of TestBench. I just commented them. I was simulating on Active-HDL software and was able to debug it. Live Update: Active HDL was set to VHDL version 2002 and was not recognizing the to_hstring function. Solve it by setting to the last version of VHDL.