sta lec37 interview question part2 | static timing analysis tutorial | VLSI

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VLSI Academy

VLSI Academy

Күн бұрын

Пікірлер: 7
@User--jm5916
@User--jm5916 Жыл бұрын
Very informative video, please share more interview questions
@DunlopJanet
@DunlopJanet 3 ай бұрын
3684 Hollis Rapid
@lenkakishore6119
@lenkakishore6119 Жыл бұрын
+ positive cross talk will improve the transition time in data path.which means reduce the delay. So + positive cross improve's setup time & degrade's hold
@hardikjain-brb
@hardikjain-brb 6 ай бұрын
improved transition time will reduce T_arrival thus hold violation
@rava951
@rava951 Жыл бұрын
Hi When can you upload signoff lv related videos (i.e PV ) ?
@ANUSHA-hl8nt
@ANUSHA-hl8nt Жыл бұрын
For setup fixing we check hold margin but due to clock push the next Data path delay increases and setup slack margin becomes more worsen in the next path so what analysis we do for setup before adding buffers in clock capture path and why we check Hold margin for setup ?
@ANUSHA-hl8nt
@ANUSHA-hl8nt Жыл бұрын
@@VLSIAcademyhub Thanks for your time and consideration.so we need to check both slack margins of setup and hold of the next path
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