STA lec8 setup time concepts - part 1 | static timing analysis tutorial | VLSI

[@pranavjain9799]

This example is actually brilliant. Thank you so much for posting this.

[@adithyanj4686]

Equation: Tsetup+Tclkq+Tcomb

[@shubhrajyoti3150]

Your content is incomparable, it's the best

[@gurazeez]

why are we subtracting skew here ? , since t2>t1, so the positive edge for the second flip flop will occur later, shouldn't that increase Trequired ?

[@aviralshrivastava2368]

ya, i had the same doubt it should add up

[@AdityaRaj-p3j]

Same doubt

[@varunjain496]

You are assuming T2 > T1. The narrator has not mentioned anywhere that T2 > T1. In the clock diagram, capture clock edge occurs before launch clock edge which means we are considering a case where T1 > T2. This is the reason we have to subtract the value from the Treq (Clock period)

[@aishwarytiwari7221]

@9:35 Why is T2 smaller than T1 (top right clock diagram) .. The down clock for capture flop should be delayed right but the launch flop clock is delayed. Isnt it giving skew as -ve ? required time should be Tclk + Ts ?

[@ursblogger3410]

Yeah

[@krzysztofherman4928]

Hi guys, what about considering the setup time of the capture FF making the equation more precise Tarrival = tckl-q + tcombo + tsetup. Kind regards, keep going making great videos.

[@DalasYoo]

Such a good example. Thank you

[@sakshigupta4579]

in presence of skew, Trequired should be Tclk-Tu right??

[@aviralshrivastava2368]

i think it'll be Tclk + Tu

[@AdityaRaj-p3j]

I think if capture clock posedge happening before launch clk then Treq will be less so Treq=Tclk-Tu and when it happens after launch clk then Treq=Tclk+Tu

[@aankitawasthi1289]

at 7:35 ,Why is T2 smaller than T1 (top right clock diagram) .. The down clock for capture flop should be delayed right but the launch flop clock is delayed.

[@aankitawasthi1289]

Here T2 is coming early and then T1 is coming.... But acc to circuit diagram....first T1 has to come and then T2 will come

[@aankitawasthi1289]

T1 is launch flop clock T2 is capture flop clock

[@tmychen354]

I have one doubt, when deriving the Trequired, why need to substract Tskew since Tuncertainty already implied the Tskew ?

[@prakashmehra3356]

uncertainity value changes in every stage . once clock tree synthesis is done , clock skew value is present . so , skew part from uncertainity is removed . you can check that placement uncertaintiy is more than post clock stage uncertainity value .

[@Narennmallya]

I had 2 doubts 1)if Tr = Tclk - Tskew -Tuncertainty, and Tuncertainty = Tskew + jitter then skew plays no role in the Required time, PROVIDED there is uncertainty in the given digital ckt? and, 2) I read somewhere that we consider 2 times jitter as it can be either before/after the clock edge, so does the equation still hold good(is it for our understanding purpose :), as in logically correct, but mathematically we need to take twice of jitter) Thanks for the course.. it genuinely helps!

[@jagannadhva8812]

Hi I guess according the point 1 skew is considered twice right ? Overall Tr = Tclk-2Tskew-jitter

[@prakashmehra3356]

it's not like that . In uncertainity a fix value of skew is assumed till place stage . because clock signal is not routed , so need to take some margin for clock skew . suppose its 50ps . Later on , tool will do clock tree synthesis and we get real clock skew , which will be different from whatever we have assumed previosuly ( 50ps) . It may higher than 50ps or , lower than 50ps as well for different paths in design . But till placement stage we assumed 50ps of clock skew for all paths , which is not true once clock signal is routed . Therefore unceratinty value will be reduced by 50ps ( or wtatever value we assumed previously) . And we will calculate real clock skew , which will be different for all paths .

[@chandusai3120]

Why we are subtract the uncertainty and skew from Time period

[@SuryadebSaha]

Hello Sir,Here skew Tsk should be added with the clk period. i.e Tclk + (Tsk) for both max and min delay.

[@VLSIAcademyhub]

Ideally skew is added to clock period. Polarity wise, If skew is positive then it gets added and if negative it gets subtracted

[@shadysworld8812]

Nice video

[@priyadogra705]

Hello sir Setup time is the maximum allowed time for data to travel from launch to capture flip flop (which means one positive edge of clock needs to be considered to travel data to capture flop) OR Setup time is the minimum amount of time the data should be held steady before clock event comes so that data is reliably sampled by clock. Which one to consider and why?

[@VLSIAcademyhub]

Actually, Both statements are same. Your first statement is with respect to clock edge, and your second statement is with respect to data edge

[@priyadogra705]

@VLSIAcademyhub isn't the first one is the definition of setup slack and second one is of setup time?

[@gabrielpimentelgomes3195]

Isn't SETUP time the time data must be stable before the capture clock edge? I'm a little confused

[@VLSIAcademyhub]

Yes you're correct

[@prakashmehra3356]

yes correct . whatever you said is correct for library setup time of the capture flip-flop . Setup Slack is the value by how much time it's failing to meet the requirement . Suppose Setup slack is 0 , it menas its arriving exactly at the time to get capture correctly . If Setup Slack is -1ps , it means isignal is arriving 1ps late

[@rajagupta7952]

TR =TCLK-TU na....Why tu itself include skew na

[@magicmuffin1]

please correct the formulas in your video. Tr =Tclk-Tu Tarrival = tckl-q + tcombo + tsetup