#STA

[@ujjwaldebbarman5556]

Why u don't consider 6ns (z) in calculation??

[@i_latebloomer101]

because 6 ns of inverter at output port is out of scope for setup time analysis ...

[@madmax6661]

Excellent video and crystal clear explanation sir, thank you for posting.

[@TechnicalBytes]

Thanks for your feedback !!

[@alvinaug3844]

Here other chip also need to operate at the same frequency right?

[@harshalthanekar4397]

If in exam the hidden chip is not there then should we consider critical path from 10ns or 7ns>8ns>9ns?

[@breathemusic5260]

Sir would like to know the source of your questions...please

[@akhilgoel2223]

Great explanation sir!!

[@TechnicalBytes]

Thanks , please keep giving your feedback on other videos as well. your likes and dislikes

[@dhanabalshanmugam7559]

Sir, Really great technical vidoes from you! I understood the importance of set_input_delay parameter when we have to do multi-FPGA designs.

[@TechnicalBytes]

you are right !!

[@MT22ECE002Shubham]

I need one month subscription but there is problem in payment process

[@TechnicalBytes]

Is your problem solved?

[@shubhamchaurasia4816]

No

[@apurvaverma3897]

I tried joining and paid 59 /mon twice but both the time it got failed. help me

[@TechnicalBytes]

But I am able to see in list of members, can you please check if you get access members perks

[@BharatIndiaHindustan628]

Very nice video sir

[@TechnicalBytes]

Hello Rohan, Thanks and glad that you liked it.

[@manveersinghmehra]

nice

[@TechnicalBytes]

Thanks

[@AbhishekSingh-up4rv]

ty

[@TechnicalBytes]

Thanks !!

[@talarikarun]

Sir can you paste link of part -1.

[@TechnicalBytes]

kzbin.info/www/bejne/bnfMZ4eEr5J6mZo

[@TechnicalBytes]

I have pasted complete play list on STA in the end screen.. please go through them

[@b-digitalb-updated3364]

Notes?

[@TechnicalBytes]

Sorry, I dont prepare any notes.