System Verilog Interview Question: Write a task to generate a clock with the given frequency in MHz?

[@Borinquen12347]

I hope you come back to make more of these videos Ken. They were very helpful in my interview prep. Thank you

[@KenIntQ]

More to come! :)

[@beenishhassan3684]

great content, look forward to more videos

[@KenIntQ]

Thanks, will do!

[@yss2685]

Thanks for a great video.

[@KenIntQ]

Glad you liked it!

[@PavanKumar-rv8pn]

good information

[@KenIntQ]

Thanks

[@openlogic925]

I think the duty cycle ratio is used in a wrong manner. If a user put 0.4 as the ratio, the period would be 80% of the intended one (0.4 high and 0.4 low, instead of 0.4 high and 0.6 low).

[@KenIntQ]

Good point.. it should always be T= 1/ F , and delay should be T * 0.5 and should not be really called duty ratio or it should be fixed to 0.5 only. I will update description accordingly. Thanks

[@zebra00024]

Why not to use #(1ps*half_period_in_ps) clk = ~clk;