Generating Custom User IP Core in Vivado

[@motassynth1507]

I don't normally comment on videos, but your series of videos on Xilinx Zynq, Vivado and Vitis tools is superb! You cover the material at the right speed and you explain all the important details. You clearly understand these complex topics very well. I have watched about 10 so far on this series. Keep up the excellent work! Thank you.

[@skabdulhaibasha3263]

simple and clear explanation. Thanks very much Vipin

[@SUPRATIKMONDAL]

But sir, in this tutorial, you have written "assign leds = slv_reg0" . But sir, here the slave registers are 32 bits but the leds has a dimension of 8 bits, so, won't there be a bit size mismatch betwee leds and slv_reg0 in the mentioned instruction?

[@chiragatreya530]

I think AXI interconnect takes care of that

[@Jocjabes]

I remember hearing for loops cannot be done in always blocks because everything needs to be executed in that cycle. But there are for loops in GPIO IP block. How do they work for example say @25:23? Thanks in advance.

[@Vipinkmenon]

This may require a long explanation. It will be incorrect to say all for loops are non-synthesizable or all for loops are synthesizable. It depends on what the loop does and how smart the EDA tools are. But all for loops which can be statically unrolled are definitely synthesizable. For example you have a memory with depth 5 and you need to initialize it to 0 when reset come always @(posedge clk) begin if(reset) begin mem[0]

[@TM-wd3pp]

@@Vipinkmenon This indeed is very interesting, specifically, that both combinational and sequential logic can be mixed in a single always block. However, in your sorting example, you are using non-blocking assignment to storeData[addr] when dataValid is high, but then are using blocking assignments for storeData[j]= and storeData[j+1]= (within the else branch). If both non-blocking and blocking assignments are made to the same storeData element, how will the tool decide whether storeData should be actual register flops or just combinational signals? Also, you are using a nested loop, to successfully implement a bubble-sort algorithm, during each iteration of the outer loop where are the results of the inner loop being held? Thank you in advance for your time, your insights are quite helpful.

[@Vipinkmenon]

One thing we need to remember is that the HDL languages (both VHDL and Verilog) were developed not with an intention for logic synthesis but with an intention of modeling and some kind of short cut for storing the schematic representation of the circuit. Later when EDA tools developed further, they were adopted as input for logic synthesis also. So like any models, they are not perfect and seems Verilog has more imperfections. Some of them are induced by the synthesis tools itself. For example as I mentioned before Xilinx's ISE tools they didn't support mixing blocking and non-blocking, which actually make sense, or dividing by any number which is not a power of 2. In Vivado both these constraints are removed. But there are still some constraints like you cannot mix edge and level triggering in sensitivity list. So always @(posedge clk or reset) begin if(reset) c

[@TM-wd3pp]

@@Vipinkmenon This was an amazing explanation and has made things crystal clear for me. I also tried your bubble-sort code with a reduced storeData array size of only 4 elements, then looked at the Elaborated design schematic in Vivado. It perfectly matched the unrolled mux/comparator combo chain logic that I had drew by hand! You have really taught me something new about Vivado, thank you!

[@Vipinkmenon]

@@TM-wd3pp Thank you.. Happy coding..

[@javeriaehsan369]

hello! where did you make the ip for reading 3 pixels at a time. I wanted to see that.

[@mohsentarashi]

Hello. How do you do? Can you help me to create a custom IP-core for SPI module on Zynq 7020??

[@amud234]

Your videos are really helpful. Could you keep a lecture on using the IP created in this video by exporting to SDK.

[@Vipinkmenon]

The next video is exactly that

[@electroready9759]

Could you tell about how netlist file is generated?

[@SUPRATIKMONDAL]

Again sir in the instruction "slv_reg1 = switches" there would be bit size mismatch because switches is of 8 bits and slv_reg1 is of 32 bits. Please clear the doubt sir.

[@kaverihatti7472]

very useful video but i request how to use the MicroBlaze and UART connection on ZYNQ board

[@jhallimisti205]

How to do the pin planning sir?

[@dheerajchumble5602]

Excellent video sir. As a beginner doesn't get it exactly which file goes where, where to edit and all that. How much it takes to reach such a proficiency....

[@Vipinkmenon]

After doing 3-4 projects should get used to it

[@dheerajchumble5602]

@@Vipinkmenon Thank you sir. Can you please suggest me some of the projects which can be done on zynq ultrascale+ mpsoc zcu104 evaluation kit and where i can get some basic tutorials regarding the same. I searched on internet, however nothing more than a 'Hello World' or single LED lowing program is there.This information will be really helpful sir

[@rux17858]

bro can you show the result on the board

[@iammituraj]

Bro can you make video with how to add interrupt to a custom IP in Vivado and use it in software?

[@Vipinkmenon]

There r many videos already in the playlist on it. Like the image processing IP