Traffic Light Controller Using Verilog (with code)| Vivado| Moore Finite State Machine

[@ArjunNarula1122]

Please find the code in the link description. Any suggestions or queries are most welcomed. PLEASE SUBSCRIBE TO THE CHANNEL. Other Projects- ►Traffic Light Controller in Verilog - kzbin.info/www/bejne/j6Wan6Jsp9x2jM0 ►Round Robin Arbiter in Verilog - kzbin.info/www/bejne/jmfSe6Ftp55gbtU ►Vedic Multiplier in Verilog - kzbin.info/www/bejne/bH6Wn6yvhsujfrc ►Clock with Alarm in Verilog - kzbin.info/www/bejne/poXOYntrZcprmKs ►Washing Machine in Verilog - kzbin.info/www/bejne/n3LSmmygid-rmas ►N bit Multiplier in Verilog - kzbin.info/www/bejne/op7ddJeua8yemrc ►PWM Shift Register in Verilog - kzbin.info/www/bejne/hqucpIOcobCjjsU

[@bharathkrishna5917]

Bro in the waveform 1 means Green, 4 means Red and 2 means Yellow. How do you say that particular number indicates particular color ? Why there is number 3 ?

[@anshumanpanigrahi7817]

@@bharathkrishna5917 We're taking binary values as RYG. So, for yellow it is 2's binary i.e, 010, for green 001, for red 100

[@ArjunNarula1122]

@@anshumanpanigrahi7817 Perfect!

[@mounikayalla9850]

Please help to simulate the test bench

[@ArjunNarula1122]

@@mounikayalla9850 Where exactly are you facing issues?

[@dumpling3309]

Thank you so much Arjun! I greatly appreciate your examples to ultimately understand Verilog HDL.

[@ArjunNarula1122]

You're most welcomed Real E. !!! Glad I could be of some help to you!

[@pranavreddy1245]

How to simulate pls tell

[@yuktasachdeva7822]

Helped in my Assignment, thankyou Arjun! Well explained

[@ArjunNarula1122]

Glad to be of some help , you're most welcomed Yukta!!!

[@pranavreddy1245]

How to simulate

[@ngoclevan2061]

I'm from Vietnam, thank you very much

[@ArjunNarula1122]

You're welcome!!!

[@Taiyab0707]

hello sir i have problem during running the code traffic_light_TB.v:12: error: Unable to bind wire/reg/memory `traffic_light_controller_TB' in `Traffic_Light_Controller_TB' 1 error(s) during elaboration. this showing i check many times but code is right i dont know why this showing

[@gudushakti99]

It is very good project and you explained in a proper manner...Thank you so much😀can you please put the video for implementation part like schematic and other things you put in the pdf please do video on it....

[@ArjunNarula1122]

Thank you for the appreciation Shakti ✨. Stay tuned for the video on implementation as well.

[@sarthaklad2738]

When are you posting the implementation video ? And also the same project can be implemented on Xilinx ISE ?

[@rajjatmmetha2335]

@Arjun Narula how to simulate it you have skipped the part in video can you please share how to simulate it I am unable to simulate it.please help me sir please.

[@ishajain949]

Amazing work ✨✨ Explanations are very nicely done!!!

[@ArjunNarula1122]

Glad you liked it!

[@atushgoel7823]

Amazing Project and very well explained.

[@ArjunNarula1122]

Thanks Atush!!!

[@HG-jl4ed]

Hey superb explanation thank you , but why there is colour initially in the waveform

[@ArjunNarula1122]

Thanks! Regarding your question I am not aware of that but will let you know as soon as I get it.

[@himanshuatri2689]

Informative video, big fan sir

[@bharathkrishna5917]

Bro I am getting high impedance as 'z' for both clk and rst. Could you please help me ?? I am using xilinx 14.2

[@shivakumarshivakumard3897]

Mee too Not getting proper output plz specify Version and Sparten which

[@madhavvaddemani7289]

bro, I have used ISE 14.1 instead of vivado. There was no errors but the TB graph was completely different from yours. what would be the reason?

[@ArjunNarula1122]

Hi Madhav , is the timescale of your graph same as the one in the video?

[@poojakadam5197]

Hello arjun nice project well done I'm getting doubt's when I go through the PDF can u make complete video of that like schematics implemention and all

[@ArjunNarula1122]

Thank you for your feedback Pooja ,I'll soon upload a video on implementation.

[@ameykhobragade5802]

tried it myself, good job

[@ArjunNarula1122]

Thank you

[@kritikasingh5106]

Hello, I tried to run this code on xilinx..on spartan 6 board..with the verilog module and test bench..but I am not getting similar waveforms as the output…I am getting red waveform. Can you please help me out.

[@ArjunNarula1122]

Kindly contact me on LinkedIn.

[@anshumanpanigrahi7817]

Hi Arjun, I'm getting red lines corresponding to M1,S,MT,M2, and the values are xxx while Simulating. Please enlighten where things are going wrong. I'm using Xilinx ISE 7.1

[@ayushshrivastava6917]

Did you find a solution to this?

[@anshumanpanigrahi7817]

@@ayushshrivastava6917 Nope bro. Did you get?

[@ayushshrivastava6917]

lol naah i looked a lot but couldn't find the solution. But I am almost sure the problem lies with how we have setup the project rather than the code.

[@anshumanpanigrahi7817]

@@ayushshrivastava6917 Yep, and I feel it's in the test bench code. Please let me know if you find the solution.

[@jayachandrakalapuppala432]

Same problem is occured but I am using xilinx ISE 14.5

[@vinayakgandhi2023]

Awesome work!!

[@ArjunNarula1122]

Thanks Vinayak ✨✨

[@ratnaprasad6522]

Hi.. Very good explanation. If u don't mind i want a small modification for this project. I stuck at one point. Can you please solve my problem. It will be more helpful to me to understand the problem. Please

[@ArjunNarula1122]

I read your message on LinkedIn , let's discuss your doubts .

[@hareelakshmiapasokarstuden1058]

Hye sir..can i know what does TMG,TY,TTG and TSG stands for please??

[@selveshwaranramesh3204]

Poi tole

[@ArjunNarula1122]

Hi, these are just the variables for the time.

[@simchawla211]

Very informative! Thanks for this.

[@maddalarachana9350]

I have a doubt why should have u been taken as (3:0) vector for count.

[@ArjunNarula1122]

We have taken (3:0) for count since we have 6 states the lower vector (2:0) would only have 4 states .

[@chrisa77]

1.Hi Arjun! a small query. How to differentiate whether it is mealy or moore FSM based on state diagram. In this case , it is written mealy(traffic light). Can we not make same project in mealy. How does state diagram change then. 2. reg count without initializing it to zero value, how code is running. Plz help. In testbench also it was started with rst=0

[@014-kotlasrinithareddy5]

Super explanation

[@maddalarachana9350]

I thinkit is (2:0)count vector.please clarify the doubt if i say wrong

[@ArjunNarula1122]

We have taken (3:0) for count since we have 6 states the lower vector (2:0) would only have 4 states .

[@mr.chiragsinghal8268]

bro can u make project in image processing in verilog

[@tahirshaik7525]

nice work man... by the way can we dump the program in spartan 3 or 3e board

[@Bgmi_Maniaa]

can you tell me how we can give coding in vivado and what are the inputs and outputs in this projects

[@ArjunNarula1122]

Regarding how to create a project and how to give inputs in vivado I'll come up with a new video.

[@sanskargemawat5600]

Heyy !! well the video was great and it has really helped us understand the logic but can you pls help me understand what constant/clock values to set to get the desired waveform bcoz I'm not getting the desired waveform and also what time to set in that !!!!!

[@sanskargemawat5600]

Also how is the ps and count appearing there?

[@anirudhmakuluri5100]

@@sanskargemawat5600 did you find any solution for this? I have the same problem.

[@sanskargemawat5600]

@@anirudhmakuluri5100 Not really!!!

[@iftekharhasnatshaon1476]

Arjun , how to extraxt files from github and use it in vivade? Any video on that?

[@adityamehta4147]

Amazing 👏👏

[@ArjunNarula1122]

Thank you 😀

[@ramkaranverma8862]

Is this a standard way to design trafic control bcz i have another way to do it without this much difficulty????

[@ArjunNarula1122]

Hi Ramkaran , this is not the standard way. I have formulated the problem statement in the first half of the video.

[@hawkeyegaming3340]

Can you explain how to simulate this in simulators?

[@ArjunNarula1122]

Please refer m.kzbin.info/www/bejne/faPWYZqgmrKDhbs

[@anujgupta-yw1ic]

I didn't understand the state table. Where are the values when its propating from s1 to s2.

[@ArjunNarula1122]

At time 07:54 when we look at the state table we can see columns of light M1 ,ME,MT and S where each of the light is represented as {RED YELLOW GREEN },for example 010 means red is off ,yellow is on and green is off. I hope this resolved your doubt. Any further questions are most welcomed .

[@shivakumarshivakumard3897]

We can use Sparten 6kit to implement the design

[@nagachoudendra5361]

Bro counter and ps waveforms are not showing,please tell

[@raeleenkanda8270]

Well done 🤩👍🏻

[@ArjunNarula1122]

Thank you 😇.

[@jatin1688]

Can we use xilinx software for simulation?

[@ArjunNarula1122]

Yes , Jatin

[@alexandru-valentinlucan7272]

can you make the same project, but in vhdl ?

[@ArjunNarula1122]

Yes Alexandru-Valentin Lucan this project can be made in vhdl as well.

[@rohansharma8210]

I am not getting count and ps in my waveform. Can you tell me how can I get it. Nice project btw!

[@ArjunNarula1122]

You might not have selected them while simulating the waveform.

[@rohansharma8210]

@@ArjunNarula1122 How to select them?

[@pranavreddy1245]

how to simulate pls tell brother

[@rakeshbykanollu5711]

Input values what should we take Bro I tried but not coming same output as in the video and in code no errors plz help me

[@rakeshbykanollu5711]

Plz tell me step by step which board we have to select and settings how to run test bench

[@rakeshbykanollu5711]

Not showing count and ps in output

[@rakeshbykanollu5711]

Plz help me bro this my mini project

[@rakeshbykanollu5711]

Plz help me

[@bathulapoojitha5418]

Hi!! I have some doubt in the state table that why you have taken 001 as green, 010 as yellow, 100 as red particularly??

[@Zahra27756]

its RYG, so for active green and other colours as inactive, its 001

[@sujithas9894]

What is the full form of ST in state table?

[@TravelandAdventure496]

where are you writing this codee

[@shivakumarshivakumard3897]

Ur test bench is showing only one state in FPGA kit

[@bharathkrishna5917]

Bro can I execute the code in Xilinx or Cadence tool ??

[@ArjunNarula1122]

Yes , Bharath

[@gowrikulkarni8340]

when i run this code it is showing error

[@sanskargemawat5600]

How to run this on EDA playground? Can you pls explain??

[@ujwalagopi4445]

I am getting an error in simulation process

[@ArjunNarula1122]

Please let me know the error by posting here.

[@ujwalagopi4445]

@@ArjunNarula1122 I get the waveform after correcting the test bench code

[@muhammadatif1972]

Hello can please send test bench

[@ruthurelectronicsinstrumen4033]

helloo. how to implement this on hardware?

[@nehapatil8505]

Is there FPGA present?

[@tanupriyagirish7525]

Hey which IEEE paper did u refer?

[@user-bu1lw7gk6u]

Hi sir great explanation sir Can u send me the documentation and ppt sir

[@ishwaryakekkarla6519]

What does it mean for M1 M2 MT S

[@ArjunNarula1122]

These are the various street lights situated on the roads. For details please refer 00:20 .

[@prateekchauhan189]

Does this project looks good in resume for companies like TI,Qualcomm

[@ArjunNarula1122]

Hi Prateek, I had this project in my resume when I got an Internship at Texas Instruments, although I would strongly recommend you not to copy the project. The sole reason for uploading it was to share the knowledge I received when I learned Verilog.

[@MSUDHANSHU]

Can we use a FPGA board?

[@ArjunNarula1122]

Yes M SUDHANSHU we can use a Basys3 board for the project.

[@ronixbhaskar8263]

Which fpga board have been used

[@ArjunNarula1122]

The default FPGA in vivado design suite.

[@ronixbhaskar8263]

@@ArjunNarula1122 so how can I do in ise

[@muhammadatif1972]

Hello sir i get error plz help me

[@ArjunNarula1122]

Hi khanoo, Can you please the error you are facing.

[@ishwaryakekkarla6519]

Hii ,I'm Ishwarya can I get the verilog code for this.

[@ArjunNarula1122]

Hi Ishwarya ,you can find the code here github.com/Arjun-Narula/Traffic-Light-Controller-using-Verilog/blob/master/Verilog%20code

[@mounikayalla9850]

Please help me to solve test bench

[@ArjunNarula1122]

Initially there's the declaration. Then I have toggled the reset and initialised the clock. Where exactly are you facing issues?

[@mounikayalla9850]

Thanks for replying the problem was solved

[@bbharath8191]

is there video for how to implement this using a fpga board?

[@hemanthbhumaraju7874]

Tool name?

[@ramyam4129]

Please I want butterfly structure coding vlsi

[@shivakumarshivakumard3897]

Objectives of this project

[@ShoaibMalik-my4bq]

How can I get it's code?

[@ArjunNarula1122]

You can find the code here github.com/Arjun-Narula/Traffic-Light-Controller-using-Verilog Do consider subscribing the channel.

[@ShoaibMalik-my4bq]

Thanks dear Arjun, It's so helpful.

[@surikoneti9591]

Bro send me pdf bro