VLSI - Lecture 3d: MOSFET Modeling - Simulating Variation

[@mvrajesh1]

Thank you sir

[@AdiTeman]

Welcome

[@鄧擎]

Have a question here. In process corner, we have conditions such as FF, SS, TT, ...etc, what is the fast or slow mean ? On the internet, some of them said it means higher (F) or lower (S) carrier mobility, others said it means MOSFET switching speed.

[@AdiTeman]

I believe that the general accepted concept of what fast and slow are come from measuring the current of a large sample of fabricated transistors and then choosing the 3-sigma point for the lowest (slow) and highest (fast) current. Then the model parameters would be curve fitted to match those currents. Therefore, many different MOS parameters would be affected, such as VT, width, length, etc. However, I can't be sure that this is the specific procedure carried out by the fab during device characterization, but conceptually, this would be close enough.

[@oncho1960]

Professor, thank you very much for the lectures! Is there a textbook you recommend?

[@AdiTeman]

The best textbook for VLSI Circuit Design is "Digital Integrated Circuits: A Design Perspective". It's getting outdated by now (from 2003), but it was amazingly forward looking so most of the concepts are still very relevant and fundamental. "CMOS VLSI Design" is a very good book, as well - much less detailed, but covers a huge amount of material and more up to date. For MOSFET modeling, read through the SPICE user manual, but a very good read is "The SPICE Book" by my friend, Prof. Andrei Vladimirescu.

[@oncho1960]

@@AdiTeman Muchas Gracias!!! Thank you very much!!!

[@debarunsaha8485]

Sir,I have a doubt on RDF in the slide 45 you explained about the RDF on two devices,what is that 170 dopants means?Can you please elaborate on that concept?.Is it the dopants in the wells or in the source /drain dopants and why only 170?..

[@AdiTeman]

Hi Devarun, I'm not sure exactly which slide you were relating to, but to answer your question. In the fabrication process (at least for planar bulk transistors, as I have elaborated upon in this lecture - not necessarily the same for FinFET and FD-SOI), there is a process step in which we dope the CHANNEL. This is the "Q_I" in the VT equation. Remember, we start with an (almost) intrinsic substrate (slightly p-type). Then we implant Source and Drain with many dopants (create N+/P+) diffusions, but our channel is "protected" by the gate at this time and therefore stays the same as the substrate (or underlying Nwell/Pwell). To then set the VT to our desired value (including HVT, LVT, etc.) we uncover the channel and implant additional dopants, but very very very few. If we needed 100 atoms added to the channel, but got 101, this has a significant effect on the VT of the transistor. By the way, in FinFET processes (and FD-SOI, as well), to the best of my knowledge, this is not done anymore, because RDF was so extreme. Other means are used to change the workfunction of the gate to channel and thereby set the desired VT level.