VLSI - Lecture 6a: Interconnect (Capacitance)

[@hardware_james5746]

I'm engineer in south korea. I admire you, and I really appreciate you beyond belief!

[@AdiTeman]

Very wonderful to hear. I have visited Seoul once (for a conference almost ten years ago) and would love to come back. Hopefully, the pandemic will pass from the world soon and we will all be able to travel freely again.

[@dongfreak]

On the coupling waveform slide (20:06), it is stated that Cagg equals Cvictim, but shouldn't it be Cc that equals Cvictim?

[@AdiTeman]

Hi, Thanks for the comment, and indeed, this is correct. But I watched the video, and I believe that is what I say (I don't think I stated that Cagg=Cvictim, but rather that Cc=Cvictim)

[@dongfreak]

@@AdiTeman thanks for your reply and I learn a lot through your lectures

[@AdiTeman]

Great to hear!

[@AbubackerSiddiquehays]

A good explanation !! Why do inductors are not considered during extraction ? Although mutual inductance could sufficiently alter the current flow in parallel wires.

[@AdiTeman]

Hi Abubacker. Generally the loops in VLSI are very small and therefore the inductance is small enough that it is insignificant in basic operation. Inductance becomes a bigger factor when moving off chip and there it is, indeed, taken into consideration.

[@netanellalazar3819]

This lecture (6a) appears twice on the course playlist

[@AdiTeman]

Fixed. Thanks.

[@زينبالريامية]

Hi Sir, Actually I`m does not understand very well about Coupling Capacitance and Delay. Could you explain to me this point.

[@AdiTeman]

Hi, I'm not sure what was not clear. But in short - a voltage change on a given net can cause a voltage change on a non connected net that has coupling to it. If the voltage change is in "the same direction" as the current transition on the net - the delay is shortened. If it is in the "opposite direction" - the delay is increased.

[@spiderman6063]

I'm a student from India working on this topic. Thanks for the knowledge. But I'm unable to download slides from your faculty page. Can you please resolve that?

[@AdiTeman]

Yes, I believe that the IT of Bar-Ilan University has put some access restrictions due to cybersecurity warnings. I will eventually move the lectures to an external server if they do not resolve this soon. Please feel free to contact me directly (e-mail) if you need a certain lecture PDF in the meantime.

[@AdiTeman]

My faculty website is back online www.eng.biu.ac.il/temanad/teaching/

[@akashwayal8797]

sir how drivers are affecting the capacitance of a wire ?

[@AdiTeman]

Hi Akash, I'm not sure I understand your question, but in general, the drivers don't (directly) affect the capacitance of the wire. The drivers are used to drive the capacitance of the wire. In other words, if I have a long wire that has a large capacitance, it would be hard for a small driver to charge/discharge it. Either enlarging the driver or breaking up the wire with repeaters or a buffer tree will improve the transition.

[@sss2393]

Can't thank you enough for this course

[@AdiTeman]

You're very welcome!

[@takshashilachunarkar4734]

Very elaborative video...I have one doubt that if I am modeling single line copper interconnect above ground line then do I have to just consider Cg value or Ctotal value from ptm interconnect model?

[@AdiTeman]

Hi, I'm not exactly sure what you are asking. If by PTM, you mean "predictive technology model" (i.e., the models often provided by Arizona State University), then they are primarily transistor models. You asked about a copper interconnect line, which is a wire, not a transistor. The wire is an RC that depends on the length/width/etc., rather than one of the parameters, such as a Cg. In any case, regarding the capacitance of the transistor, this depends on what state it's in and how it is connected to decide which capacitances are relevant, but in many CMOS type designs, connections are to the gate and are dominated by Cg (though this is, by all means, not the case always).