Techniques to Reduce Power

[@asharanisamal7400]

One of the best teacher I have came across. All of his videos are so simple and easy to understand.

[@kshubham1]

Kitne pyar se sir ne teach kiya hai maza aa gaya

[@anupammathur17]

really helpful lectures!!

[@sdeepak6555]

Very useful lecture.. thanks for uploading!

[@paavnishukla]

Teachers like him are needed for the much needed clarity on VLSI basics . Really really grateful

[@優さん-n7m]

This is the blessing of the holy cow

[@souadechikh8843]

Hello dear Professor , I appreciate you a lot for all your courses that are preparing for us to help us for growing in our research well,I would like to ask you some questions under 128Bit eFuse IP Design subject Problem statement: creating a convenable circuit that satisfied these specifications - Supply voltage: VDD=2.2V - VIO=5.5VTemperature:-40C 25 C to 125C Operating Mode :Program/Program Verify-Read/Read Program. -Program Verify Read:10k (PVR Mode) - Read Mode :5k {Read_Programmed Cell& Read_Uprogrammed Cell - Current :

[@dhaneshdprabhu8482]

I like the way you teach. Complex but makes the understanding so each. The course or verilog, arm and now VLSI, all are amazing. Thanks swayam and nptel for this priceless gift

[@sajankumar-ry6lt]

arm? i cant find those

[@dhaneshdprabhu8482]

@@sajankumar-ry6lt Look for Embedded Systems with ARM. I think it's in some from IIT KGP

[@kabandajamir9844]

The world's best teacher thanks sir

[@YashN009]

got v good basics knowledge about leakage reducing techniques. Thanks for the video

[@優さん-n7m]

Why does reducing the supply voltage, I mean the VDD, result in the circuit becoming slower.

[@優さん-n7m]

Why use OR gate and not AND gate for clock gating, what am I missing here?

[@anupammathur17]

He's using the disable signal, so when the disable signal goes high, the output of the OR gate becomes high which might disable the clk from the ckt, where as when the disable signal is set low, the ckt works in the normal mode.

[@lakshmi-kb4ww]

Thankyou so much sir. Great explanation

[@優さん-n7m]

This is lecture 59, please put this into the video text

[@優さん-n7m]

The transistors with lower Vth have higher leakage current, how come?

[@優さん-n7m]

adaptive body biasing (abb) and dynamic threshold scaling (dts), never heard of them before.

[@surendralodhi8997]

you told that static power can be reduced if we selectively use low thresold nMOS and pMOS devices, but we know that for LVT cells leakage will be more. so we should use HVT cells instead of LVT right?

[@vkskaushal]

true

[@iammituraj]

but HVT cells have higher dynamic power diss. So use HVT cells at chip regions having lesser switching activity.

[@kabandajamir9844]

So nice thanks sir

[@PROGAMER-lu1nm]

Sir is from Computer science department and he is telling VLSI . It's great to hear from such people ☺️

[@ManjitSingh-wl8pn]

Can u provide ppt

[@優さん-n7m]

When transistors are stacked, won't each of them have its very own leakage current since they are all powered up so they can conduct? If they are never powered then how can they ever conduct? I did not get the part about the transistor stacking to reduce the leakage power.