What is the difference between 1 and 1'b1 in Verilog ? || Concatenation Problems { }

we should be aware of the difference in length , of the literals we use . In this video I discussed about 1 vs 1'b1 , and the problems caused by them , especially in concatenation.
#programming #vlsi #verilog #electronic
🔗 Resources :
- stackoverflow.com/users/35355...
- stackoverflow.com/users/59000...
- stackoverflow.com/users/27556...
🔥 Thanks for watching , Have any doubts comment down , happy to help you. Please Do Subscribe .

[@dcocz3908]

It was the digbee that got me

[@AshishPatel-vy7mn]

For big designs, we can use open source linting tool verilator, it will give warnings which the compiler doesn't.

[@tientranmanh798]

I agree with you that we must know exactly bit width of each member of concatenation operator (both RHS and LHS) and should not directly use a integer value. However, we're lucky again that compiler will yell an error message "illegal use of a constant without an explicit width specification" when you try to put "1" into concatenation. I use Cadence Xcelium.

[@KarthikVippala]

Yup

[@nantes9807]

I love your chanel man, which is the best book to learn verilog please ?

[@KarthikVippala]

Thank you so much🙏, verilog - Samir Palnitkar, Digital design - Anand kumar, My favourite ,advance chip design by kishore mishra, hope it's helpful

[@nantes9807]

@@KarthikVippala I appreciate it. can I have another question, Is there any book for systems Verilog?

[@KarthikVippala]

System verilog - Chris spears . Verification guide on google