13.14. Asynchronous FIFOs

[@ShivamKumar-ky6vm]

nice explianation , very helpful for UARTS

[@junaid_kadannappalli]

Do you have verilog code and explanation of that project. If yes please post it. Thanks

[@electrontube4284]

I don't do Verilog coding, only VHDL. But you will find thousands of hits for code for a simple asynchronous FIFO if you google it. This is a pretty common block.

[@NostalgiaT]

whats the use of encoder and decoder, why do we use it?

[@carterlee287]

hi, Thanks for great video. I'm trying to understand asynchronous fifo. especially Gray encoded counter synchronized number is not have a consistency. for example) always @(posedge rclk or negedge rrstn) if (!rrstn) { rq2_wgray, rq1_wgray } 03->02->06->07->05->04... rq1_wgray value change as 00->01->06->04... (Skipped 03->02 and 07->05 Because of rclk) Here, I don't understand why wgray encoded by GRAY code? As I know, Gray encode counter is for Glitch and Metastbility. It should be changed with only one bit. But rq1_wgray values skipped some number meaning that it does not change with only one bit. explain this? What is purpose "gray encoding counter" especially at Here(wgray)? What happens some skipped value in rq1_wgray. Gray counter's some numbers skipped . this is violation of introducing about Gray encoding to resolve metastability. What do you think about this?

[@NostalgiaT]

whats the difference between asynchronous and sysnchrounos?