FIFO Clock Domain Crossing (CDC) | FIFO Basics | Asynchronous FIFO | Synchronous FIFO | FIFO Design

Hello Everyone, In this Video I have explained about FIFO Basics i.e. What is FIFO?, Why do we need FIFO, Types of FIFOs, Asynchronous FIFO, Synchronous FIFO, FIFO Write pointer, FIFO Read pointer, FIFO address calculation, Gray Code importance, Gray code pointers.
Keywords:
First in First Out, FIFO, FIFO Design Basics, How to design FIFO, How to Design Synchronous FIFO, How to Design Asynchronous FIFO, FIFO Depth Calculation, FIFO full condition, FIFO empty condition, CDC of multibit signals, Clock Domain Crossing of Data signals, Clock Domain Crossing of Multibit signals, Clock Domain Crossing of Multibit data, CDC techniques, clock domain crossing interview questions, clock domain crossing techniques, clock domain crossing synchronizer, CDC vlsi, vlsi interview questions, digital design, digital electronics, nptel, metastability in vlsi, metastability, Multibit synchronizer, Gray code synchronizer, Gray code in CDC, Electronicspedia, Electronicspedia latest video,
Chapters :
00:00 - Introduction
01:47 - What is FIFO?
03:27 - Why we need FIFO?
06:52 - Types of FIFO
07:24 - Why Asynchronous FIFO is required?
10:12 - Gray Code Importance in CDC
11:17 - Binary to Gray code conversion
14:43 - FIFO Basics
21:00 - FIFO Full condition
23:00 - FIFO Empty Condition
#FIFO #AsynchronousFIFO #SynchronousFIFO #FIFObasics #FIFOdesign #VLSI
Credits:
1. A Magical Journey Through Space by Leonell Cassio | / leonellcassio
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Creative Commons Attribution-ShareAlike 3.0 Unported
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[@Electronicspedia]

Please Like, Share and Subscribe to my channel kzbin.info/door/3mTACG8vPWsHQFMfxzeDZg

[@katiaraniabitam7714]

Thank you for your efforts !!

[@Vidyashreers]

Great explanation!!

[@Anithachintala]

Hi sir, you mentioned we will add 1 once pointers reaches to 7th location we compare MSB bits. Lets consider my both pointers are rolled overed onve so their msbs are 1 and if write pointer again reached to 7th location and read pointer is still at 0th location now when we compare msbs even if we add 1 to write pointer it will be still 1 and read pointer is also having 1 as msb due to previous full condition. Please clariy sir how to compare full condition in this case

[@akhilkumar.podugu]

Valuable !

[@Electronicspedia]

Thank you. 😊

[@kamalapurammaheswar2854]

is it possible to add half empty / hall full condition. if so how can we add that particular condition.

[@hemantsaxena369]

Is there any way to manage continuous input data using FIFO

[@hemantsaxena369]

How to manage continuous incoming data, I mean without burst how depth of FIFO has to be calculated

[@zarnapatel4442]

how can we verify circular fifo..?

[@garrisongreenwood3144]

Not very good. Uses “push” and “pop” to describe FIFO read/write operations when these terms are associated with stack memory operations. Could be a source of confusion.

[@cyrillemagdi7717]

I did not get the condition at which we consider the FIFO emtpy. Why didn't we say {~rptr[3], rptr[2:0]} == {wrptr[3:0]} Like we did with FULL Condition??

[@Electronicspedia]

This is because, write will happen first then only we can read data. Read will try to catch the write pointer.

[@cyrillemagdi7717]

@@Electronicspedia Got it, Thank you

[@lakshya_garg]

Great explanation!

[@Electronicspedia]

Thank you 😊

[@pranavgupta4552]

Why we moved to synchronous fifo and asynchronous fifo, it's not very clear in video??

[@Electronicspedia]

I didn't get your question correctly. Synchrnous FIFO : We use this when the two clocks on both read and write side are same but the interval of writing(speed) and reading is different Asynchronous: When there is a write and read frequency are different and we want to transfer continuous stream (finite length) of multibit data, we usually use Asynchronous FIFO. Please let me know if there is some confusion

[@pranavgupta4552]

@@Electronicspedia thanx for reply. My question is Why we need sync. & Async. Fifo ?? Or which drawback motivates us to use these fifo either sync. Or async ?

[@joon2402]

@@pranavgupta4552 Some designs require you to use two different clocks for a FIFO. If it is the same clock, nothing is really difficult..

[@enisyuksel5525]

I have a question, sorry if it's silly :) Suppose pixel data comes from a camera (512x640). After that we can save this data in array ( line buffer[511:0] ). Then we can send these data to the desired data bus, respectively. (line[0],line[1],line[2]....line[512]). Why use FIFO when we can do this? My second question, async design is recommended when there are different clocks. But what I don't understand is if I save the data at the clock speed I want, why would the speed of the read process affect this? The writing process is already finished.

[@Electronicspedia]

Hi Enis, My understanding from your question is that you are working on a synchronous clock. i.e. both read and write frequency are same. Now assume if you are writing data every clock cycle on 100MHz, and the read is happening on the same clock frequency but every alternative clock cycle. This means there is a data rate change but frequency is same. In this case you need synchronous FIFO. Otherwise the you may missout write data. I hope this answers your both queries. Do let me know.

[@enisyuksel5525]

@@Electronicspedia Hello :) First of all, thank you for your reply. I will describe exactly what I want to do to better explain my problem. 10-21 Mhz values ​​(I get parallel pixel data from my camera with CMOS standard). Normally, as the simplest logic, I was aiming to store this data in a buffer and then add some packets to the beginning and give them serially (200Mhz) to the output port (MIPI CSI-2). Later I saw in diagrams that the data was recorded with FIFO. Then, while I was doing research, I discovered your channel and questions started to form in my mind. With your permission, I would like to consult you. 1-) First of all, I am trying to understand why FIFO is needed. I guess the answer is to read and process data faster while writing it without waiting for the transmission to finish. Otherwise, it's easier to save the data in an array and read it when the transmission is finished. (Please verify me or point out what I'm thinking wrong) 2-) If we are not going to read and write at the same time or if we are going to read and write at the same time and at the same speed, I think there is no problem. The problem is that we read and write at the same time, but read and write at different clock speeds. (When I say at the same time, I mean to start reading all the data without waiting for the recording to finish). I guess in this case we need to design asynchronous FIFO. Am I thinking wrong? If it is wrong, what is the correct one, what do you think master?

[@Electronicspedia]

In your first case, how are you reading it, what is the frequency? Is it the same as write frequency (10-21Mhz)?

[@enisyuksel5525]

​@@Electronicspedia The camera's pixel clock depends on the mode selected. I will use it for 2 mods. One is 10.519Mhz, the other is 21.04Mhz. If you are going to give an example to explain the logic, you can accept the frequency you want. At this frequency, the data will come in parallel and I will have to save the incoming data by sharing the clocks. I guess that's the writing process. Later, when I want this data, I need to serialize it quickly, for example at 200Mhz.

[@Electronicspedia]

Hi Enis, 1. When there is a write i.e. pixel data coming from the Camera, this data will be stored in FIFO(Asynchronous) and then Read back if in read frequency is different compared to write. Your understanding is correct here. 2. When there is a write i.e. pixel data coming from the Camera, and if you believe that there wont be any subsequent data coming from Camera till you process the current data and send out serially, Then You may not need FIFO. It is as good as you are creating a back pressure to the Camera, that do not send new Pixel data. 3. For the above point 2, The CDC tools might give CDC violations, as data is crossing the two clock boundaries. You need to add waiver or you need add constraints. 4. If the Point 2 is NOT true, then You may have to add a FIFO, so that you do not miss out the incoming data.

[@cyrillemagdi7717]

What if the read pointer is pointing at for example the 3rd location and the wrptr became equal to the rptr which means they are equal and the FIFO is FULL, this time the Most Significant Bit of the wrptr will not be equal to 1, How will we consider the FULL Condition in that case ?

[@Electronicspedia]

I didn't get your question correctly. What's the depth of fifo you are considering is it 4, From 0 to 3? If read pointer is at 3, and write pointer is catching up the read pointer, then it means the write pointer has already rolled over once, so it's MSB bit will be different than read pointer's MSB. As soon as write pointer reaches read pointer value, full condition will be flagged

[@cyrillemagdi7717]

@@Electronicspedia The same depth as the one in the video, From 0 to 7 (3 bits)

[@Electronicspedia]

My above comment still holds true even if the depth is 7 or 8

[@cyrillemagdi7717]

@@Electronicspedia Thanks a lot