Advanced Process Technologies - Part 5: Current Trends

[@94D33M]

Thanks ALOT. These indepth videos are rarely found on youtube. Pure gem.

[@AdiTeman]

Glad you think so!

[@johnnyBrwn]

Thanks. Literally unbelievable you're giving this out for free. I'll be a genius by the time I watch all your playlist.

[@AdiTeman]

I'm so glad to be able to provide you with knowledge!

[@SharathSatheesh]

Thank you soo much for these amazing lectures! It felt like a refresher course to my microlectronics post graduation course I completed back in 2014.

[@AdiTeman]

Glad to hear!

[@aniket2812]

Thank you for these rare semiconductor related videos. I work at GlobalFoundries and these videos are great source of information...

[@AdiTeman]

Wonderful to hear and I would be happy to learn from you as well, as I have never had the opportunity to work at a fab or be "up close and personal" with this stuff :)

[@SigitYuwono]

very nice serie of lectures

[@AdiTeman]

Thanks!

[@thulasireddy8265]

Thank you , very informative

[@AdiTeman]

You're welcome!

[@vikassh9875]

Thankyou so much.

[@AdiTeman]

You're welcome!

[@ctnrb741]

Thank you so much. This was really great!

[@AdiTeman]

You're so welcome!

[@maddyjenkins192]

Really amazing series, learnt a lot! I have a question regarding GAA, how do the number of litho patterning layers change at the transistor level with this new architecture? (From what I understand the FinFet has the fin, the cut and the via and then also x3 for the gate?)

[@AdiTeman]

Hi Maddy, Actually, I am far from a process engineer or a litho engineer, so I have no good answer for you. In fact, I have never myself been involved in any type of fabrication - all my knowledge comes from things I've read or heard and "good guesses" I've made based on experience designing circuits. That being said, I want to point out that there are many many many litho steps for the front end of the line. It's not just one litho step for fin, cut and via. It's many steps that may even be considered a "secret sauce" of the fab. In fact, the majority of the processing time of the wafer is spent during the front end stages and this "gives time" for the design team to send out a so-called "metal fix", in case a bug is found (...or a feature added) in between tapeout and when the back end process starts. It may sound crazy, since you're not allowed to make any changes to the bottom layers in between, but by using "Bonus cells" and or by just rerouting the design (while the transistors are fixed in place), you can fix things after tapeout. And again, this is because transistor fabrication is a long and complex process with many steps. How many - I can't tell you and the fab won't - but it's a lot!

[@harirao12345]

Outstanding

[@AdiTeman]

Thanks

[@harirao12345]

Thank you Professor! This is outstanding! Do you have a link to “Finfet Process Overview” by Nahum. 🙏

[@AdiTeman]

No, actually this was an internal presentation that he gave, and while he allowed me to use his material (and helped me create this lecture), he asked not to share his original slides.

[@hemantp66]

very good and informative

[@AdiTeman]

Thank you!

[@sagarkore9648]

Thank you sir :)

[@AdiTeman]

Most welcome!

[@ndjarnag]

good

[@AdiTeman]

Thanks