DVD - Lecture 10: Packaging and I/O Circuits

[@expectopatronum21]

Myself being a Mask Design Engineer , I appreciate your in-depth knowledge of IC packaging . Quite informative !

[@AdiTeman]

Thanks for watching!

[@AnandBharti]

Very deep understanding and explained nicely. Impressive.

[@AdiTeman]

Many thanks!

[@yulongutk]

The best IC packaging I/O lecture I ever seen!

[@AdiTeman]

Thank you!

[@boopathyj6805]

Quality Of the Slides & lecture is awesome. I consider myself lucky to get landed in your Channel. Thanks

[@AdiTeman]

Great to hear!

[@rahulbhat3409]

Thank you so much for these lectures, truly an amazing series.

[@AdiTeman]

You're very welcome! And great questions!

[@boyanzhang3782]

Learn a lot from you. Truly appreciated!

[@AdiTeman]

You're very welcome!

[@chayan7758]

THANK YOU FOR THE SERIES OF VIDEO, THOROUGHLY ENJOYED AND TOOK NOTE OF IT TOO.

[@AdiTeman]

Glad you enjoyed it!

[@chandradesu1052]

Exceptional lectures

[@AdiTeman]

Thanks!!!

[@BerkeleyLiang]

Hi, Prof. Adam Teman. I am interested in the flip-chip packaging part. Can we place I/O pads inside a chip instead of on the edges when using C4 bumps? At 20:45, we can see a photo with pads on the edges, and the RDL connects pads to bumps inside the chips. I wonder whether it is necessary. Or just because the design of the certain chip used I/O pads on the edges. Resolved at 44:20. "Yes, we can."

[@AdiTeman]

Yes, there is no physical reason that you cannot put I/O circuits in the middle of the chip. But there are practical reasons that the periphery is still the primary location of the I/Os. The two main reasons I can think of off the top of my head are: 1) The Power Rings - you need to provide power rails to I/Os for level shifters and ESD protection and therefore you need to feed 4 rails into an I/O (Digital VDD/VSS and I/O VDD/VSS). We generally supply these through power pads that connect to the I/O rings. So to put an I/O somewhere, you need an additional 4 I/Os (power supply I/Os) to feed its rails. This is quite a bit of overhead if you're not providing this to a bunch of I/Os. Therefore, if you do put I/Os in the middle of the chip, you will usually have a bunch of them (e.g., a bus) 2) They disrupt the overall floorplan. The I/Os are routed up to the top metal (RDL) to get to the bumps. So they are essentially blocking all the routing resources above them and to route from one side to the other, you'd have to detour around the I/O. This is inconvenient and can cause congestion. When the I/Os are on the periphery, this is a non-issue. Probably there are additional reasons, but these are some of the main ones. Therefore, most of the internal connections are just power supplies, where you highly benefit from connecting directly from a bump to an internal part of the chip core.

[@praneethd.shetty3197]

Thank you very much sir...for all the videos...very much useful 🤩🙌🙌🤝🤝

[@AdiTeman]

Thanks for your kind words.

[@bharatnalluri1609]

Good one

[@yewedmund]

Great lecture series! Will you be able to record the english version of the last lecture "Chip Finalizing and Sign-Off"?

[@AdiTeman]

Yes. In fact, I have to teach it in a few weeks at Bar-Ilan University and I will record it in English before I teach the lecture in class.

[@Negedge]

Hi, are the digital IO Pad released in the foundry library ? No need to extra purchase, right?

[@AdiTeman]

Usually they are but not necessarily. Most foundries will provide you with basic IPs: standard cells, I/Os and an SRAM compiler. But this is not part of the process design kit (PDK), and not part of the standard cell library, but rather a separate IP library. Therefore, you can purchase the I/O library from a different vendor (or get more advanced I/Os from the foundry) or design them yourself. In the end, they're "just" a circuit, so you can for sure design them in-house.

[@Negedge]

@@AdiTeman thanks for your reply, and your lecture help me a lot, remarkable work!!

[@Negedge]

It's me again, can vdds connected together in package, will that cause problem in high frequency scenario?

[@AdiTeman]

This should not cause a problem. The lines on the board are wide with very low resistance. That being said, high-frequency board and package design is a very non-trivial (high price!) thing, and I am far from being an expert. But in general, connecting and shorting together the power supplies in as many places possible is the best thing you can do.

[@Negedge]

@@AdiTeman thanks for your answer, I am finding out a clue why chip's working current lower than my expected current, maybe because IR drop failure or the package bonding wire disconnected 🤔~

[@andriibulatov63]

Dear Adam Teman, greetins. What if a chip has few different power domains, is it possible to use few "semi" rings for reducing total amount of rings?

[@AdiTeman]

Multiple power domains are beyond the scope of this course - I hope I will have time to prepare a few lectures on this in the future. However, to try and answer your question (I didn't fully understand what you mean), you would usually make a local ring around the power domains and feed it directly from the voltage source (regulator or pad)

[@mridulverma9441]

Hi Adam, Can you upload the lectures in the PD series in english. Thanks

[@AdiTeman]

Hi Mridul. Could you please elaborate? Which "PD series" are you referring to? This is lecture 10 in the series that is recorded in English. Unfortunately, I will not have time to re-record the lectures in my other courses in the near future, though I plan to do it sometime.

[@KavitaSharma-wm7wq]

@@AdiTeman he is talking about Physical design "PD"

[@VDNhat]

Thannks

[@AdiTeman]

You're welcome!