Can Set Up and Hold Time be negative? | STA | Back To Basics

Can Set Up and Hold Time be negative? | STA | Back To Basics
Is Set up and hold time of a flip flop always positive or is it possible to have zero and negative set up and hold requirements? Watch this video to know the answer.
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• D-Latch & D-Flip flop.
Find all my videos on Physical Only Cells in the following playlist.
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#SetUp#Hold#BackToBasics

[@niroshaj.r.1730]

Mam can u do next videos on sdc contents , static and dynamic power Dissipations please

[@nikhilkake7931]

I think you missed telling which one is danger either setup -ve or hold -ve. And if u given conclusion as setup -ve value is accepted but not for hold. Nice explanation, easily understand for freshers. :)

[@balakrishnareddybanda5769]

Can i get u number

[@hakobmanukyan8233]

You were explaining very well

[@064chilukuriaditya3]

super understood it very clearlyy

[@avinashvinith84]

It was a very good explanation.

[@backtobasics5602]

Thanks :)

[@doepic8147]

Mam please make a video on end cap cell.

[@emipushpam9417]

Nice explanation.

[@subhamnayak4726]

excellent ma'am

[@sharathreddyvancha1577]

If clock is delayed, then the transmission gate will be turned after 5 ns and the data can be transferred only after TG is turned On and the setup time will be 3ns right, the clock delay can only cancel out delay due to Scanin combinational logic. It doesn't affect the original setup time. Correct me if I missed something

[@ayushsrajput301]

Thanks a lot 😁

[@shashankkhope2289]

can addition of hold and setup time be negative?

[@mohangowda4282]

hi mam , there is a typo error in last slide , it should be hold not setup for last two conditions

[@rohitkumarthakur2793]

Can u make video on calculation of derate

[@rajdeepvartak7826]

But this data combination logic is outside flip-flop then how we will consider if for negative hold flip flop?

[@sivasiitb]

It can be 0 but not negative. Unless the clock is there how the gate opens and reach both the inverters?

[@guruprasadreddy7570]

excellent madam👏

[@DalasYoo]

I just wonder how the setup time negative related to the skew. When seeing the timing report, we always tell that the negative skew is violation. Isn't this same meaning to have setup time negative?

[@pavantv749]

I can say we get negative clock skew due to routing path of clock for the two consecutive flipflops

[@sathwikpothana2184]

How can setup time and hold time can chage they being constants?? I believe rather saying setup and hold time negative we should say hold slack and setup slack can be negative. Correct me if iam wrong.

[@jahnuchoudhury6677]

Ma'am .. here Cp is the clock path delay for the clock of first transmission gate... and transmission gate in the loop has no clock path dalay... am I right ??

[@rohitkumarthakur2793]

Good explanation

[@ajaykodipelli8617]

Hi Mam.. does negative and zero values of setup and hold, violates the functionality

[@udayv1301]

0:12 without any further delay hahaha

[@uday5786]

can u expain in timing analysis

[@govindmr1984]

always we will get only setup violation but hold violations come into picture after cts ? why

[@backtobasics5602]

Hold only comes into picture when the clock tree gets built, due to skew, since skew is the major cause of hold violations. Since the clock is ideal in place(skew will be 0), there won't be significant hold violations at place.

[@KavitaSharma-wm7wq]

How to calculate setup time for any flop .. where we can find the setup value for particular flop.?

[@lokeshamara2788]

From the lookup tables in .lib file, setup_time or hold time =f(data_transition,clock_transition)

[@seelamnarendrareddy8982]

Can you tell about sdc file

[@travelfreakphani5933]

pichikeka